Nonvolatile semiconductor memory device

• US 20070235793A1
• Filed: 03/20/2007
• Published: 10/11/2007
• Est. Priority Date: 03/21/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Takano, Tamae, Yamazaki, Shunpei, Asami, Yoshinobu
• Granted Patent: US 8,729,620 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises a semiconductor material and has an energy gap which is smaller than an energy gap of the semiconductor layer.

2. The nonvolatile semiconductor memory device according to claim 1, wherein a difference between the energy gap of the semiconductor layer and the energy gap of the floating gate is greater than or equal to 0.1 eV.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

5. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

6. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

7. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

8. The nonvolatile semiconductor memory device according to claim 1, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has the same conductivity type as a conductivity type of the pair of impurity regions.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

11. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

12. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer has an electron affinity which is larger than an electron affinity of the semiconductor layer.

13. The nonvolatile semiconductor memory device according to claim 12,

wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

14. The nonvolatile semiconductor memory device according to claim 12, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

15. The nonvolatile semiconductor memory device according to claim 12, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

16. The nonvolatile semiconductor memory device according to claim 12, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

17. The nonvolatile semiconductor memory device according to claim 12, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

18. The nonvolatile semiconductor memory device according to claim 12, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

19. The nonvolatile semiconductor memory device according to claim 12, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has the same conductivity type as a conductivity type of the pair of impurity regions.

20. The nonvolatile semiconductor memory device according to claim 12, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

21. The nonvolatile semiconductor memory device according to claim 12, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

22. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and

wherein a barrier energy for an electron of the first layer of the floating gate, which is formed by the first insulating layer, is higher than a barrier energy for an electron of the semiconductor layer, which is formed by the first insulating layer.

23. A nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

24. A nonvolatile semiconductor memory device according to claim 22, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

25. The nonvolatile semiconductor memory device according to claim 22, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

26. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

27. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

28. The nonvolatile semiconductor memory device according to claim 22, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

29. The nonvolatile semiconductor memory device according to claim 22, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has the same conductivity type as a conductivity type of the pair of impurity regions.

30. The nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

31. The nonvolatile semiconductor memory device according to claim 22, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

32. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises germanium or a germanium compound.

33. The nonvolatile semiconductor memory device according to claim 32, wherein the germanium compound is germanium oxide or germanium nitride.

34. A nonvolatile semiconductor memory device according to claim 32, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

35. A nonvolatile semiconductor memory device according to claim 32, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

36. The nonvolatile semiconductor memory device according to claim 32, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

37. The nonvolatile semiconductor memory device according to claim 32, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

38. The nonvolatile semiconductor memory device according to claim 32, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

39. The nonvolatile semiconductor memory device according to claim 32, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

40. The nonvolatile semiconductor memory device according to claim 32, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has the same conductivity type as a conductivity type of the pair of impurity regions.

41. The nonvolatile semiconductor memory device according to claim 32, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

42. The nonvolatile semiconductor memory device according to claim 32, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.

43. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel forming region between a pair of impurity regions which are formed apart from each other;

a first insulating layer over the channel forming region;

a floating gate over the channel forming region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the floating gate includes at least a first layer which is in contact with the first insulating layer and a second layer formed over the first layer, and the first layer comprises germanium or a germanium compound and has a thickness of greater than or equal to 1 nm and less than or equal to 20 nm.

44. The nonvolatile semiconductor memory device according to claim 43, wherein the germanium compound is germanium oxide or germanium nitride.

45. A nonvolatile semiconductor memory device according to claim 43, wherein the first insulating layer comprises a layer in which a silicon oxide layer and a silicon nitride layer are sequentially stacked from the semiconductor layer side.

46. A nonvolatile semiconductor memory device according to claim 43, wherein the semiconductor layer is an island-like semiconductor layer formed on an insulating surface.

47. The nonvolatile semiconductor memory device according to claim 43, wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

48. The nonvolatile semiconductor memory device according to claim 43, wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

49. The nonvolatile semiconductor memory device according to claim 43, wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

50. The nonvolatile semiconductor memory device according to claim 43, wherein an edge of the floating gate in a channel width direction is provided over the semiconductor layer and an impurity region having a conductivity type which is different from a conductivity type of the pair of impurity regions.

51. The nonvolatile semiconductor memory device according to claim 43, wherein the semiconductor layer comprises a low-concentration impurity region which overlaps with the floating gate and has the same conductivity type as a conductivity type of the pair of impurity regions.

52. The nonvolatile semiconductor memory device according to claim 43, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the floating gate is in contact with the silicon nitride layer.

53. The nonvolatile semiconductor memory device according to claim 43, wherein the first insulating layer comprises a silicon oxide layer formed by a plasma treatment to the semiconductor layer and a silicon nitride layer formed by a plasma treatment to the silicon oxide layer.