SELF-ALIGNED BODY CONTACT FOR A SEMICONDCUTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME

• US 20070235801A1
• Filed: 04/04/2006
• Published: 10/11/2007
• Est. Priority Date: 04/04/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Divakaruni, Ramachandra, Cheng, Kangguo
• Granted Patent: US 7,439,135 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

Claims

1. A method of forming a contact;

comprising;

forming set of mandrels on a top surface of a substrate, each mandrel of said set of mandrels arranged on a different corner of a polygon and extending above said top surface of said substrate, a number of mandrels in said set of mandrels equal to a number of corners of said polygon;

forming sidewall spacers on sidewalls of each mandrel of said set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of said polygon, a region of said substrate exposed in said opening;

etching a contact trench in said substrate in said opening; and

filling said contact trench with an electrically conductive material to form said contact.

2. The method of claim 1, further including:

removing said sidewall spacers.

3. The method of claim 1, further including;

recessing said electrically conductive material below said top surface of said substrate and forming in said contact trench, an insulating layer on said electrically conductive material.

4. The method of claim 1, wherein said substrate is a silicon substrate and includes a buried oxide layer separating said substrate into an upper silicon layer on a top surface of said buried oxide layer and a lower silicon layer under said buried oxide layer.

5. The method of claim 4, wherein said etching said contact trench in said substrate in said opening includes:

etching said contact trench through said upper silicon layer and said buried oxide layer into said lower silicon layer.

6. The method of claim 4, further including:

forming an n-channel field effect transistor (NFET) or a p-channel field effect transistor (PFET) in said upper silicon layer, said contact electrically connecting a body of said NFET or a body of said PFET to said lower silicon layer.

7. The method of claim 4, further including

forming a device trench in said substrate;

and

forming a vertical NFET or a vertical PFET in said device trench, a first source or drain of said vertical NFET or said vertical PFET formed adjacent to said top surface of said buried oxide layer in said upper silicon layer and a second source or drain of said NFET or said PFET formed adjacent to said top surface of substrate in said upper silicon layer.

8. The method of claim 4 further including:

forming a device trench in said substrate;

forming a trench capacitor and forming a gate of a vertical NFET or a vertical PFET in said device trench, said gate and said trench capacitor electrically and physically separated by a dielectric cap formed in said device trench, said gate extending from said dielectric cap through said upper silicon layer and said trench capacitor extending into said lower layer of said substrate; and

forming a first source or drain of said vertical NFET or said vertical PFET adjacent to said top surface of said buried oxide layer in said upper silicon layer and forming a second source or drain of said NFET or said PFET adjacent to said top surface of substrate in said upper silicon layer.

10. The method of claim 1, wherein each mandrel of said set of mandrels comprises a gate of a vertical n-channel field effect transistor or a gate of a p-channel field effect transistor formed in a device trench formed in said substrate.

11. The method of claim 1, wherein a thickness of said sidewall spacers measured perpendicular to sidewalls along said top surface of said substrate of said mandrels is greater than half a minimum distance between a furthest apart pair of adjacent mandrels.

9. The method of claim 9, further including:

forming a buried electrically conductive strap between said first source or drain of said vertical NFET or said vertical PFET and a plate of said trench capacitor, said plate formed inside said device trench.

12. A method of forming a dynamic access memory cell, comprising:

forming a pad layer on a top surface of a semiconductor-on-insulator substrate, said substrate including a buried insulating layer separating said substrate into an upper semiconductor layer between a top surface of said buried insulating layer and said top surface of substrate and a lower semiconductor layer;

forming a set of device trenches, each device trench extending from a top surface of said pad layer, through said upper semiconductor layer, through said buried insulating layer and into said lower semiconductor layer;

forming a dielectric layer on sidewalls of said device trenches and filling said device trenches with an electrically conductive first fill material to a level below said a top surface of said buried insulating layer to form a trench capacitor;

forming a buried electrically conductive strap around each of said devices trenches in said buried insulating layer and forming sources or drains in said upper semiconductor layer adjacent to said buried strap;

forming a first insulating cap over said first fill material;

forming a gate dielectric on sidewalls of said device trenches above said first fill material;

filling said device trenches with an electrically conductive second fill material to form vertical gates;

removing said pad layer to expose mandrels comprising regions of said vertical gates extending above said top surface of said substrate;

forming sidewall spacers on sidewalls of said mandrels, said sidewall spacers merging with each other and forming an unbroken ring around a region of said substrate;

etching a contact trench through said upper semiconductor layer, said buried insulating layer and into said lower semiconductor layer in said region of said substrate not covered by said sidewall spacers;

filling said contact trench with an electrically conductive third fill material and recessing said third fill material below said top surface of said substrate but above said top surface of said buried insulating layer;

forming in said contact trench, a second insulating cap over said third fill material and forming an electrically conductive cap over said second insulating cap; and

removing said sidewall spacers and forming sources or drains in said upper semiconductor layer around said device trenches adjacent to said top surface of said upper semiconductor layer.

13. The method of claim 12, further including:

forming diffused regions around the bottoms of said device trenches to form diffused plates of said trench capacitors.

14. The method of claim 12, further including:

before forming said sidewall spacers, forming a protective cap on top of said vertical gates in said device trenches; and

removing said protective cap immediately before or after said removing said sidewall spacers.

15. The method of claim 12, wherein each device trench of said set of device trenches is arranged on a different corner of a polygon.

16. The method of claim 12, further including:

forming a spacer on sidewalls of said contact trench before filling said contact trench with said third fill material, said spacer allowing carriers to pass through.

17. The method of claim 16, further including:

removing said spacer from upper regions of said sidewalls of said contact trench not protected by said third fill material before forming said second insulating cap.

18. The method of claim 12, further including:

forming a top insulating layer on a top surface of said substrate and co-planarizing top surfaces of said vertical gates and a top surface of said insulating layer.

19. The method of claim 18, further including:

forming a wordline on a top surface of said top insulating layer, said wordline electrically and physically contacting at least one of said vertical gates.

20. The method of claim 19, further including:

forming an electrically conductive contact to said upper semiconductor layer.

21. An electronic device, comprising:

a semiconductor on insulator substrate, said substrate including a buried insulating layer separating said substrate into an upper semiconductor layer between a top surface of said buried insulating layer and said top surface of substrate and a lower semiconductor layer;

at least three vertical field effect transistors (FETs), each of said three or more FETs having a body formed in said upper semiconductor layer, a gate extending from said top surface of said substrate, a first source/drain formed around said gate adjacent to said top surface of said upper semiconductor layer and a second source drain formed around said gate adjacent to said buried insulating layer; and

a body contact formed in said substrate between said at least three vertical FETs, said body contact self-aligned to all of said gates of said at least three vertical FETs, said body contact extending above and below said buried insulating layer and electrically connecting said upper semiconductor layer to said lower semiconductor layer.

22. The device of claim 21, wherein said three or more vertical FETs are vertical NFETs.

23. The device of claim 21, wherein said three or more gates are arranged at the corners of a polygon.

24. The device of claim 21, further including:

at least three corresponding trench capacitors formed in said lower semiconductor layer aligned under said vertical FETs, said trench capacitors each comprising an electrically conductive first plate surrounded by a dielectric layer and said dielectric layer surrounded by an electrically conductive second plate; and

buried straps formed in said buried insulating layer and electrically connecting said second source/drain of corresponding vertical FETs to corresponding first plates of said trench capacitors.

25. The device of claim 24, further including:

a bitline contact to said first source/drain of at least one of said at least three vertical FETs; and

a wordline in physical and electrical contact with at least one gate of said at least three vertical FETs.

26. The device of claim 24, further including:

a dielectric cap on top of said buried body contact, said dielectric cap extending from a top surface of said buried body contact toward but not to said top surface of said substrate;

and an electrically conductive strap formed in said upper semiconductor layer on top of said dielectric cap and electrically connecting two first source/drains of different vertical FETs of said at least three vertical FETs, said source/drains extending from said top surface of said substrate deeper into said upper semiconductor layer than said strap.

27. The device of claim 21, further including a spacer on sidewalls of said contact trench.

28. The device of claim 27, wherein said spacer is silicon nitride or silicon carbide with a thickness ranging from 5 to 20 angstroms.

29. The device of claim 24, wherein said at least three vertical FETs includes four vertical FETs arranged over the corners of a four-sided diamond pattern.

30. The device of claim 24, wherein said first and second sources drains, said buried straps, said strap and said first plates are doped N-type and said upper semiconductor layer and said body contact are doped P-type.