INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NET SPACER

• US 20070235846A1
• Filed: 04/01/2006
• Published: 10/11/2007
• Est. Priority Date: 04/01/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Ha, Jong-Woo, Park, Soo-San, Lee, Sang-Ho
• Granted Patent: US 7,829,986 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An integrated circuit package system that includes forming a strip level net spacer including support bars, tie bars and paddles. Configuring the support bars, the tie bars and the paddles to form open regions and interconnecting the support bars, the tie bars and the paddles to provide structural support to vertically stacked semiconductor devices.

Claims

1. An integrated circuit package system comprising:

forming a strip level net spacer including support bars, tie bars and paddles;

configuring the support bars, the tie bars and the paddles to form open regions; and

interconnecting the support bars, the tie bars and the paddles to provide structural support to vertically stacked semiconductor devices.

2. The system as claimed in claim 1 further comprising:

providing an adhesive layer on the bottom of the paddles.

3. The system as claimed in claim 1 wherein:

interconnecting the support bars, the tie bars and the paddles provides structural support to second semiconductor devices formed over first semiconductor devices during attachment and wire bonding.

4. The system as claimed in claim 1 wherein:

forming the strip level net spacer includes forming the strip level net spacer of plastic or heat dissipating material.

5. The system as claimed in claim 1 further comprising:

configuring the strip level net spacer to prevent warping of a substrate.

6. An integrated circuit package system comprising:

providing a substrate with first semiconductor devices interconnected to the substrate;

providing a strip level net spacer including paddles used for supporting second semiconductor devices, tie bars which interconnect the paddles to support bars, and open regions between the paddles, the tie bars and the support bars; and

providing the second semiconductor devices over the first semiconductor devices and supported by the paddles.

7. The system as claimed in claim 6 further comprising:

interconnecting the first semiconductor devices and the second semiconductor devices to the substrate via wire bonding.

8. The system as claimed in claim 6 further comprising:

providing an adhesive layer on the bottom of the paddles for bonding to the first semiconductor devices.

9. The system as claimed in claim 6 wherein:

providing the substrate with the first semiconductor devices includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

10. The system as claimed in claim 6 wherein:

providing the second semiconductor devices includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

11. An integrated circuit package system comprising:

a substrate with a first semiconductor device interconnected to the substrate;

a strip level net spacer including a paddle, tie bars which interconnect the paddle to support bars, and open regions between the paddle, the tie bars and the support bars; and

a second semiconductor device over the first semiconductor device and the paddle.

12. The system as claimed in claim 11 further comprising:

an adhesive layer on the bottom of the paddle.

13. The system as claimed in claim 11 wherein:

the support bars, the tie bars and the paddle provide structural support to the second semiconductor device that prevents delamination and chip cracking.

14. The system as claimed in claim 11 wherein:

the strip level net spacer is formed of plastic or heat dissipating material.

15. The system as claimed in claim 11 wherein:

the strip level net spacer prevents warping of a substrate.

16. The system as claimed in claim 11 further comprising:

the first semiconductor device and the second semiconductor device interconnected to the substrate via wire bonding.

17. The system as claimed in claim 16 wherein:

the first semiconductor device includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

18. The system as claimed in claim 16 wherein:

the second semiconductor device includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

19. The system as claimed in claim 16 wherein:

the strip level net spacer includes a plurality of the paddles;

the substrate includes a plurality of the first semiconductor devices; and

the integrated circuit package system includes a plurality of the second semiconductor devices.

20. The system as claimed in claim 16 further comprising:

an adhesive layer on the bottom of the paddles for bonding to the first semiconductor devices.