Semiconductor die packages using thin dies and metal substrates

• US 20070235886A1
• Filed: 04/06/2006
• Published: 10/11/2007
• Est. Priority Date: 04/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yilmaz, Hamza, Wang, Qi, Li, Minhua, Sapp, Steven, Murphy, James, Diroll, John
• Granted Patent: US 7,768,075 B2
• Time in Patent Office: Days
• US Class Current: 257/779
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Claims

1. A semiconductor die package comprising:

a metal substrate;

a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture, wherein the metal substrate is attached to the second surface; and

a plurality of conductive structures on the semiconductor die, wherein the plurality of conductive structures includes at least one first conductive structure disposed on the first surface of the semiconductor die, and at least one second conductive structure disposed in the at least one aperture,

wherein the at least one second conductive structure is in electrical communication with the second terminal at the second surface of the semiconductor die.

2. The semiconductor die package of claim 1, further comprising a mechanical layer attached to the metal substrate, wherein the metal substrate is between the mechanical layer and the semiconductor substrate.

3. The semiconductor die package of claim 1, wherein the semiconductor die comprises a power transistor, wherein the first electrical terminal is an input terminal and the second electrical terminal is an output terminal.

4. The semiconductor die package of claim 1, wherein the semiconductor die has a thickness less than about 50 microns and wherein the metal substrate has a thickness greater than about 50 microns.

5. The semiconductor die package of claim 1, wherein the conductive structures are solder bumps.

6. The semiconductor die package of claim 1, wherein the conductive structures are plated metal layers.

7. The semiconductor die package of claim 6, further comprising solder on the plated metal layers.

8. The semiconductor die package of claim 1, wherein the semiconductor die is a first semiconductor die and wherein the semiconductor die package comprises a second semiconductor die, wherein the second semiconductor die is attached to the metal substrate.

9. The semiconductor die package of claim 1, further comprising a first metal layer on the first surface of the semiconductor die, and a second metal layer overlapping the first metal layer, wherein the second metal layer and the first metal layer are electrically isolated from each other and wherein the first metal layer is electrically coupled to the at least one second conductive structure.

10. The semiconductor die package of claim 1, wherein the semiconductor die comprises a power MOSFET, wherein the first terminal is a source terminal in the power MOSFET, and the second terminal is a drain terminal in the power MOSFET, and wherein the first surface of the semiconductor die comprises a gate terminal.

11. An electrical assembly comprising:

the semiconductor die package of claim 1;

and

a circuit board, wherein the semiconductor die package is mounted to the circuit board.

12. A method comprising:

obtaining a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, wherein the metal substrate is attached to the second surface of the semiconductor die;

forming at least one aperture in the semiconductor die, thereby exposing a portion of a surface of the metal substrate; and

depositing at least one conductive structure in the at least one aperture, wherein the at least one conductive structure is in electrical communication with the metal substrate.

13. The method of claim 12 further comprising attaching a mechanical layer to the metal substrate, wherein the metal substrate is between the mechanical layer and the semiconductor substrate after attachment.

14. The method of claim 12 wherein the semiconductor die comprises a power transistor, wherein the first terminal is an input terminal and the second terminal is an output terminal.

15. The method of claim 12 wherein the semiconductor die has a thickness less than about 50 microns and wherein the metal substrate has a thickness greater than about 50 microns

16. The method of claim 12 wherein the conductive structures are solder bumps.

17. The method of claim 12 further comprising depositing at least one conductive structure on the first surface of the semiconductor die, the at least one conductive structure being in electrical communication with the first terminal.

18. The method of claim 12 wherein forming at least one aperture comprises etching the semiconductor die.

19. The method of claim 12 wherein depositing at least one conductive structure comprises electroplating.

20. The method of claim 12 wherein after depositing, a semiconductor die package is formed, and wherein the method comprises:

mounting the semiconductor die package to a circuit board.

21. A method comprising:

obtaining a semiconductor die comprising a first surface comprising a source terminal, a second surface including a drain terminal, wherein the metal substrate is attached to the second surface of the semiconductor die, and wherein the semiconductor die has a thickness of less than about 50 microns;

forming at least one aperture in the semiconductor die, thereby exposing a portion of a surface of the metal substrate; and

depositing at least one conductive structure in the at least one aperture, wherein the at least one conductive structure is in electrical communication with the metal substrate.