Test method, semiconductor device, and display

• US 20070236244A1
• Filed: 06/01/2007
• Published: 10/11/2007
• Est. Priority Date: 07/22/2003
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ando, Naoki
• Application Number:
  US11/809,458
• Publication Number:
  US 20070236244A1
• Time in Patent Office: Days
• US Class Current: 324/760.10
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The present invention allows an efficient test as to the presence of line defects in data lines and gate lines in a liquid crystal display. A logic circuit for a test is provided according to the interconnect layout structure on a semiconductor substrate of a liquid crystal display, and ends of data lines are coupled to inputs of the logic circuit. At the time of the test, test drive signals corresponding to a certain logical value are applied to the data lines, and a determination is made as to defects in the data lines based on the output from the logic circuit, obtained in response to the signal application. This way means that determinations can be made as to defects in the data lines based on a logical value as the output from the logic circuit, i.e., binary values. Such a configuration is also applied to gate lines.

Claims

1. A test method for a semiconductor substrate in which pixel cell drive circuits each including a pixel switch and a pixel capacitor that is coupled to the pixel switch and holds pixel data are arranged in a matrix corresponding to intersections between data lines and pixel switch control lines, the method comprising:

a drive step of driving the data line or the pixel switch control line as a test target with a test drive signal that has a required voltage level; and

a comparison step of comparing an output level of a potential that arises in the data line or the pixel switch control line driven by the test drive signal, with a reference level to which a certain level is assigned, and outputting a comparison result as a logical value.

2. A semiconductor device comprising, on a semiconductor substrate:

an image display area in which pixel cell drive circuits each including a pixel switch and a pixel capacitor that is coupled to the pixel switch and holds pixel data are arranged in a matrix corresponding to intersections between data lines and pixel switch control lines;

drive means for driving the data line or the pixel switch control line as a test target with a test drive signal that has a required voltage level; and

comparison means for comparing an output level of a potential that arises in the data line or the pixel switch control line driven by the test drive signal, with a reference level to which a certain level is assigned, and outputting a comparison result as a logical value.

3. A display comprising:

a semiconductor substrate;

a counter substrate having a common electrode that is disposed to face the semiconductor substrate; and

a liquid crystal layer disposed between the semiconductor substrate and the counter substrate, wherein the semiconductor substrate includes;

drive means for driving the data line or the pixel switch control line as a test target with a test drive signal that has a required voltage level; and

comparison means for comparing an output level of a potential that arises in the data line or the pixel switch control line driven by the test drive signal, with a reference level to which a certain level is assigned, and outputting a comparison result as a logical value.