MINIMIZING TIMING SKEW AMONG CHIP LEVEL OUTPUTS FOR REGISTERED OUTPUT SIGNALS
First Claim
Patent Images
1. A synchronous output buffer circuit comprising:
- a first output register configured to latch a first input signal in response to an output clock signal, and thereby provide a first output signal;
a second output register configured to latch a second input signal in response to the output clock signal, and thereby provide a second output signal;
an output driver directly connected to receive the first and second output signals from the first and second output registers, and in response drive an output signal on an output terminal of the synchronous output buffer;
combinational logic configured to provide the first and second input signals in response to a first set of signals used to implement a first output function and a second set of signals used to implement a second output function, different than the first output function, wherein the combinational logic is located entirely within one or more pipes that lead into the first and second output registers.
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Abstract
A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.
14 Citations
27 Claims
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1. A synchronous output buffer circuit comprising:
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a first output register configured to latch a first input signal in response to an output clock signal, and thereby provide a first output signal;
a second output register configured to latch a second input signal in response to the output clock signal, and thereby provide a second output signal;
an output driver directly connected to receive the first and second output signals from the first and second output registers, and in response drive an output signal on an output terminal of the synchronous output buffer;
combinational logic configured to provide the first and second input signals in response to a first set of signals used to implement a first output function and a second set of signals used to implement a second output function, different than the first output function, wherein the combinational logic is located entirely within one or more pipes that lead into the first and second output registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A synchronous output buffer circuit comprising:
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a first output register configured to latch a first input signal in response to an output clock signal, and thereby provide a first data signal;
a second output register configured to latch a second input signal in response to the output clock signal, and thereby provide a second data signal;
combinational logic configured to provide the first and second data signals in response to a first set of signals used to implement a first output function, the combinational logic further configured to provide a first test signal and a second test signal in response to a second set of signals used to implement a second output function, different than the first output function, wherein the combinational logic is included entirely within one or more pipes that lead into the first and second output registers;
a first multiplexer configured to route the first data signal or the first test signal as a first output signal in response to a mode signal;
a second multiplexer configured to route the second data signal or the second test signal as a second output signal in response to the mode signal; and
an output driver directly connected to receive the first and second output signal from the first and second multiplexers, and in response drive an output signal on an output terminal of the synchronous output buffer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification