CIRCUIT TO OPTIMIZE CHARGING OF BOOTSTRAP CAPACITOR WITH BOOTSTRAP DIODE EMULATOR

• US 20070236283A1
• Filed: 04/05/2007
• Published: 10/11/2007
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Locatelli, Christian, Francesco Merello, Andrea
• Granted Patent: US 7,456,658 B2
• Time in Patent Office: Days
• US Class Current: 327/589
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having a high- and a low-side driver circuits for driving high- and low-side switches connected at a switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and a low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing supply voltage for the high-side driver circuit. The optimizing circuit includes a first switch connected to the first terminal of the bootstrap capacitor; and a phase sense comparator for sensing the voltage at the switched node and turning ON the first switch when the voltage at the switched node is LOW, whereby charging of the bootstrap capacitor is optimized when the phase sense comparator is enabled.

Claims

1. A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having a high- and a low-side driver circuits for driving high- and low-side switches connected at a switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and a low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing a supply voltage for the high-side driver circuit, the optimizing circuit comprising:

a first switch connected to the first terminal of the bootstrap capacitor; and

a phase sense comparator for sensing the voltage at the switched node and turning ON the first switch when the voltage at the switched node is LOW, whereby charging of the bootstrap capacitor is optimized when the phase sense comparator is enabled.

2. The optimizing circuit of claim 1, wherein the bootstrap diode emulator circuit further comprises a dynamic back-gate biasing circuit connected to the bootstrap capacitor.

3. The optimizing circuit of claim 1, wherein the first switch has lower forward losses than a diode.

4. The optimizing circuit of claim 1, wherein the bootstrap diode emulator circuit further comprises a gate control circuit for driving the first switch;

and a dynamic back-gate biasing circuit.

5. The optimizing circuit of claim 1, further comprising an emulator driver circuit connected to a control terminal of the first switch for controlling the first switch, wherein the phase sense comparator and the emulator driver are connected between a low side supply voltage and a ground potential, and the first switch is series connected between the low side supply voltage and the high side floating supply voltage.

6. The optimizing circuit of claim 1, wherein the phase sense comparator receives an enabling signal generated by a low side output pre-driver from a low side input signal and provides an output signal VSsense out to the low side driver.

7. The optimizing circuit of claim 6, wherein the phase sense comparator is disabled when a high side input signal is HIGH and enabled when the low side input signal is HIGH, the HIGH low side input signal forces the enabling signal HIGH.

8. The optimizing circuit of claim 7, further comprising a time out circuit responsive to the high a low side input signals, and wherein, when the timeout circuit is operative, with the high and low side input signals being OFF,

the phase sense comparator is enabled and the first switch is turned ON if the switched node voltage stays OFF or decreases to a DC−

level, and

the phase sense comparator is disabled and the first switch is turned OFF if the switched node voltage stays at or rises to DC+level.

9. The optimizing circuit of claim 8, wherein the timeout is approximately one microsecond.

10. The optimizing circuit of claim 8, wherein the phase sense comparator remains enabled if at the end of the timeout the phase of the voltage VS is LOW and turns OFF if the voltage VS goes HIGH.

11. The optimizing circuit of claim 10, wherein the phase sense comparator provides a double enable for charging the bootstrap capacitor by turning ON the bootstrap diode emulator

when the low side driver input is ON, and

when the switched node voltage is LOW.