Programming method to reduce word line to word line breakdown for NAND flash

• US 20070236990A1
• Filed: 03/28/2006
• Published: 10/11/2007
• Est. Priority Date: 03/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,561,469 B2
• Time in Patent Office: Days
• US Class Current: 365/185.10
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.

Claims

1. A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:

applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming in the NAND architecture non-volatile memory array;

selecting one or more intermediate pass voltages between the program voltage and a pass voltage;

applying each of the one or more intermediate pass voltages to a word line of a set of one or more adjacent word lines, wherein the set of one or more adjacent word lines are physically adjacent the selected word line; and

applying the pass voltage to one or more remaining unselected word lines of the string.

2. The method of claim 1, wherein the method of programming is one of a self boost programming operation, a drain-side self boost programming operation, and a local self boost programming operation.

3. The method of claim 2, wherein the method of programming is a drain-side self boost programming operation and where selecting one or more intermediate pass voltages between the program voltage and a pass voltage further comprises selecting the one or more second intermediate pass voltages between the program voltage and a blocking cell word line voltage to set a selected voltage differential for one or more intervening word lines of the memory array that are between the selected word line and the blocking cell word line.

4. The method of claim 3, further comprising selecting and applying one or more third intermediate pass voltages between the blocking cell word line voltage and the pass voltage to set a selected voltage differential for one or more second adjacent word lines of the memory array that are on an opposite side of the blocking cell word line from the selected word line.

5. The method of claim 2, wherein the method of programming is a local self boost programming operation and where selecting one or more intermediate pass voltages between the program voltage and a pass voltage further comprises selecting one or more second intermediate pass voltages between the program voltage and a blocking cell word line voltage to set a selected voltage differential for one or more intervening word lines of the memory array that are between the selected word line and a first and second blocking cell word lines, where the first and second blocking word lines are on opposite sides of the selected word line on the string.

6. The method of claim 5, further comprising selecting and applying one or more third intermediate pass voltages between the blocking cell word line voltage and the pass voltage to set a selected voltage differential for one or more second adjacent word lines of the memory array that are on an opposite side of the first and second blocking cell word lines from the selected word line.

7. The method of claim 1, wherein selecting one or more intermediate pass voltages between the program voltage and a pass voltage further comprises selecting one or more intermediate pass voltages between the program voltage and a pass voltage to set a selected voltage differential between adjacent word lines of the memory array.

8. The method of claim 1, wherein selecting one or more intermediate pass voltages between the program voltage and a pass voltage further comprises selecting one or more intermediate pass voltages between the program voltage and a pass voltage to set a selected field strength across the insulation between adjacent word lines of the memory array.

9. The method of claim 1, wherein the non-volatile memory cell is one of a floating gate memory cell, a multi-level cell (MLC), and a non-conductive floating node memory cell.

10. The method of claim 1, wherein selecting one or more intermediate pass voltages between the program voltage and a pass voltage further comprises selecting one or more intermediate pass voltages between the program voltage and a pass voltage based on one of a relative cross section of the selected word line and the one or more adjacent word lines and an insulating oxide thickness between the selected word line and the one or more adjacent word lines.

11. A method of operating a NAND architecture memory device, comprising:

applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in a NAND architecture non-volatile memory array of the memory device;

applying a first pass voltage to one or more unselected word lines of the string; and

applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are adjacent to the selected word line.

12. The method of claim 11, wherein the programming operation is one of a self boost programming operation, a drain-side self boost programming operation, and a local self boost programming operation.

13. The method of claim 11, wherein applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage further comprises applying one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a desired maximum voltage differential between adjacent word lines of the memory array.

14. The method of claim 11, wherein applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage further comprises applying one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a selected field strength across the insulation between adjacent word lines of the memory array.

15. The method of claim 11, wherein the non-volatile memory cell is one of a floating gate memory cell, a multi-level cell (MLC), and a non-conductive floating node memory cell.

16. The method of claim 11, wherein applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage further comprises applying one or more second pass voltages that are selected from between the program voltage and the first pass voltage, where the one or more second pass voltages are selected based on one of a relative cross section of the selected word line and the one or more adjacent word lines and an insulating oxide thickness between the selected word line and the one or more adjacent word lines.

17. A non-volatile NAND architecture memory device comprising:

a NAND architecture non-volatile memory array having a plurality of memory blocks; and

a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by,

applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in a NAND architecture non-volatile memory array of the memory device,

applying a first pass voltage to one or more unselected word lines of the string, and

applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are adjacent to the selected word line.

18. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to program memory cells by one of a self boost programming operation, a drain-side self boost programming operation, and a local self boost programming operation.

19. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to apply one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a desired maximum voltage differential between adjacent word lines of the memory array.

20. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to apply a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage further comprises applying one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a selected field strength across the insulation between adjacent word lines of the memory array.

21. The non-volatile NAND architecture memory device of claim 17, wherein the memory cells are one of floating gate memory cells, multi-level cells (MLCs), and non-conductive floating node memory cells.

22. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to apply one or more second pass voltages that are selected from between the program voltage and the first pass voltage based on one of a relative cross section of the selected word line and the one or more adjacent word lines and an insulating oxide thickness between the selected word line and the one or more adjacent word lines.

23. A system comprising:

a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,

a NAND architecture non-volatile memory array having a plurality of blocks;

wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by,

selecting one or more memory cells in one or more NAND architecture memory cell strings for programming in the selected block of non-volatile memory cells, where the one or more selected memory cells in each of the one or more memory cell strings is coupled to a selected word line,

applying a program voltage to the word line coupled to the one or more selected memory cells,

applying a first pass voltage to one or more unselected word lines of the one or more memory cell strings, and

applying a second pass voltage to one or more adjacent unselected word lines of the one or more memory cell strings, wherein the second pass voltage is selected to be between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are physically adjacent to the selected word line.

24. The system of claim 23, wherein the host is one of a processor and a memory controller.

25. The system of claim 23, wherein the system is adapted to program memory cells by one of a self boost programming operation, a drain-side self boost programming operation, and a local self boost programming operation.

26. The system of claim 23, wherein the system is adapted to apply one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a desired maximum voltage differential between adjacent word lines of the memory array.

27. The system of claim 23, wherein the system is adapted to apply a second pass voltage to one or more adjacent unselected word lines of the one or more strings, wherein the second pass voltage is between the first pass voltage and the program voltage further comprises applying one or more second pass voltages that are selected from between the program voltage and the first pass voltage to set a selected field strength across the insulation between adjacent word lines of the memory array.

28. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory device comprises;

a NAND architecture non-volatile memory array having a plurality of memory blocks,

wherein the memory module is adapted to program memory cells in a selected block of the non-volatile memory array by,

applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in the memory array of the memory device,

applying a first pass voltage to one or more unselected word lines of the string, and

applying a second pass voltage to one or more adjacent unselected word lines of the string, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are physically adjacent to the selected word line.

29. The memory module of claim 28, further comprising a memory controller coupled to the one or more memory devices for controlling operation of each memory device in response to the host system.

30. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein the memory module is adapted to program memory cells in a selected block of at least one of the memory devices by,

applying a program voltage to a selected word line coupled to one or more memory cells of one or more NAND architecture memory strings that selected for programming in the selected block of the memory device,

applying a first pass voltage to one or more first unselected word lines of the one or more strings, and

applying a second pass voltage to one or more second unselected word lines of the one or more strings, wherein the one or more second unselected word lines are adjacent to the selected word line and the second pass voltage is between the first pass voltage and the program voltage.