Methods and apparatus for improved memory access

• US 20070237009A1
• Filed: 05/29/2007
• Published: 10/11/2007
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Ring Technology Enterprises of Texas LLC (IPNav)
• Inventors: Lynch, William, Herbison, David
• Granted Patent: US 7,808,844 B2
• Time in Patent Office: Days
• US Class Current: 365/189.120
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 7/1036 using data shift registers

Abstract

A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Claims

1-54. -54. (canceled)

55. An apparatus, comprising:

a data input/output port;

a connection circuit, connected to the input/output port;

a shift register that shifts according to a shift clock signal, connected to the connection circuit;

wherein the connection circuit loads data from the input/output port into the shift register after shift data is loaded into the shift register and before the shift data is shifted out of the shift register, such that the shift register shifts without interruption according to the shift clock signal.

56. The apparatus of claim 55, wherein the data input/output port is an input/output port of a memory device.

57. The apparatus of claim 55, wherein the connection circuit loads the data according to a signal derived from the shift clock signal.

58. The apparatus of claim 55, wherein the shift register is part of a shift register chain.

59. The apparatus of claim 55, further comprising:

a transmission bus, wherein an output of the shift register is connected to the transmission bus.

60. The apparatus of claim 59, wherein the transmission bus is connected to one of a group comprising:

a processor, a selector, a fiber optic connector, a routing channel, and a switching fabric.

61. An apparatus, comprising:

a data input/output port;

a connection circuit, connected to the input/output port;

a shift register that shifts according to a shift clock signal, connected to the connection circuit;

wherein the connection circuit loads a copy of shifted in data from the shift register to the input/output port before the shifted in data is shifted out of the shift register, such that the shift register shifts without interruption according to the shift clock signal.

62. The apparatus of claim 61, wherein the data input/output port is an input/output port of a memory device.

63. The apparatus of claim 61, wherein the connection circuit loads the data according to a signal derived from the shift clock signal.

64. The apparatus of claim 61, wherein the shift register is part of a shift register chain.

65. The apparatus of claim 61, further comprising:

a transmission bus, wherein an output of the shift register is connected to the transmission bus.

66. The apparatus of claim 65, wherein the transmission bus is connected to one of a group comprising:

a processor, a selector, a fiber optic connector, a routing channel, and a switching fabric.