Hybrid DC-offset reduction method and system for direct conversion receiver

• US 20070237264A1
• Filed: 04/05/2006
• Published: 10/11/2007
• Est. Priority Date: 04/05/2006
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: ISSC Technologies Corporation (Microchip Technology Incorporated)
• Inventors: Huang, Kuang-Hu, Peng, Wei-Chung, Chuan, Chia-So
• Granted Patent: US 7,933,361 B2
• Time in Patent Office: Days
• US Class Current: 375/332
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A hybrid structure circuit for the cancellation of both Type-I and Type-II DC offsets. It comprises a static compensator in conjunction with a servo-loop feedback amplifier to suppress the undesired DC components present along the path of the base band after the direct conversion mixer. Two mixers are used to down convert a received RF signal directly to a base band signal with two components: in-phase and quadrature-phase. Both in-phase and quadrature-phase branches employ the same circuitry for DC offset cancellation. Miller effect is also utilized in the structure in order to implement the circuit on-chip.

Claims

1. An RF receiver circuit for reducing static and dynamic offsets, comprising of:

a low noise amplifier (LNA);

a plurality of down conversion mixers;

a plurality of static compensators coupled to the down conversion mixers;

a plurality of constant gain stages coupled to the compensators;

a plurality of channel-select low-pass filters connected to the constant gain stages;

a plurality of servo-loop feedback amplifiers connected to the channel-select low pass filters;

a gain mapping block driving the servo-loop feedback amplifiers;

a plurality of analog to digital converters; and

an automatic gain feedback control block driving the LNA and the gain mapping block.

2. The RF receiver circuit of claim 1, wherein the down conversion mixers comprises of an in-phase mixer and a quadrature-phase mixer.

3. The RF receiver circuit of claim 1, wherein the analog to digital converters (ADC) comprises of a quadrature-phase ADC and an in-phase ADC.

4. The RF receiver circuit of claim 1, wherein the static compensators comprises of an in-phase static compensator and a quadrature-phase static compensator.

5. The RF receiver circuit of claim 1, wherein the servo-loop feedback amplifiers comprises of an in-phase servo-loop feedback amplifier and a quadrature-phase servo-loop feedback amplifier both driven to the gain mapping block.

6. The RF receiver circuit of claim 1, wherein each of the static compensators comprises of:

a subtractor;

a digital to analog converter (DAC);

a first register;

a second register;

a controller; and

a comparator.

7. The RF receiver circuit of claim 1, wherein each of the servo-loop feedback amplifiers comprises of:

a plurality of subtractors;

a plurality of variable gain amplifiers; and

a plurality of low pass filters.

8. The RF receiver circuit of claim 1, wherein the gain mapping block assigns the gain for each stage in the servo-loop feedback amplifiers in such a way as to use the maximum gain of an earlier stage before assigning the unsatisfied gain to the remaining stages.

9. The RF receiver circuit of claim 8, wherein the plurality of servo-loop feedback amplifiers includes three amplifiers connected in a three-stage configuration, the first amplifier having a maximum gain of G_max,1, the second amplifier having a maximum gain of G_max,2, and the third amplifier having a maximum gain of G_max,3, and wherein the gain mapping block allocates gain G₁ to the first amplifier, gain G₂ to the second amplifier, and gain G₃ to the third amplifier such that the total target gain for the three-stage amplifier G is distributed according to the following conditions:

if G<

=G_max,1, then setting G₁=G, G₂=0, and G₃=0;


if G>

G_max,1 and G<

=(G_max,1+G_max,2), then setting G₁=G_max,1 and G₂=G−

G_max,1, and G₃=0; and


if G>

(G_max,1+G_max,2) and G<

=(G_max,1+G_max,2+G_max,3), then setting G₁=G_max,1, G₂=G_max,2, G₃=G−

(G_max,1+G_max,2).

10. The RF receiver circuit of claim 1, further comprising an overload detection circuit having an input and an output, the input connected from the channel-select low pass filters and the output connected to the automatic gain feedback control block.

11. The RF receiver circuit of claim 1, wherein Miller capacitance is utilized in the servo-loop feedback amplifiers.

12. The RF receiver circuit of claim 6, wherein the digital to analog converter (DAC) has a capacity of 5-8 bits.

13. An RF receiver comprising a servo feedback loop and a static offset reduction circuit, wherein the digital to analog converter (DAC) in the static offset reduction circuit is 5-8 bits.

14. A method for amplifier gain allocation to reduce DC offset in an N-stage servo-feedback variable gain amplifier, wherein the target total gain for the N-stage amplifier is C, the maximum gain in each stage is G_max,1, G_max,2, . . . , G_max,N, respectively, and the gain setting to each stage is G₁, G₂, . . . , G_N, respectively, the method comprising the following steps:

if G<

=G_max,1, then setting G₁=G and G_i=0 for i=2, . . . , N;


if G>

G_max,1 and G<

=(G_max,1+G_max,2), then setting G₁=G_max,1 and G₂=G−

G_max,1, and G_i=0 for i=3, . . . , N;


if G>

(G_max,1+G_max,2) and G<

=(G_max,1+G_max,2+G_max,3), then setting G₁=G_max,1, G₂=G_max,2, G₃=G−

(G_max,1+G_max,2), and G_i=0 for i=4. . . , N; and

Continuing assigning the maximum remaining gain to the first available stage until the desired target gain G is satisfied.

15. The method for amplifier gain allocation as recited in claim 14, wherein N=3, and wherein the target total gain for the 3-stage amplifier is G, the maximum gain in each stage is G_max,1, G_max,2, G_max,3, respectively, and the gain setting to each stage is G₁, G₂, G₃, respectively, the method comprising the following steps:

if G<

=G_max,1, then setting G₁=G, G₂=0, and G₃=0;


if G>

G_max,1 and G<

=(G_max,1+G_max,2), then setting G₁=G_max,1 and G₂=G−

G_max,1, and G₃=0; and


if G>

(G_max,1+G_max,2) and G<

=(G_max,1+G_max,2+G_max,3), then setting G₁=G_max,1, G₂=G_max,2, G₃=G−

(G_max,1+G_max,2).

16. A method for DC offset reduction for an RF receiver including a low-noise amplifier (LNA), an automatic gain control (AGC) circuit, servo-loops for dynamic DC offset reduction, and a static DC offset reduction circuit, the method comprising:

resetting the AGC;

disabling the servo-loops;

setting initial gains for the variable gain amplifiers in the servo-loops and the LNA;

enabling servo-loops;

releasing AGC;

setting a delay time to allow servo-loops to settle its gain settings;

adjusting gains of LNA; and

freezing the AGC.

17. A method as recited in claim 16, wherein servo-loop gains are set such that maximum gain is assigned to the earliest stages.

18. A method as recited in claim 16, wherein the delay time is about 100 to 200 ns.