Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor

• US 20070238250A1
• Filed: 03/30/2006
• Published: 10/11/2007
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhang, Da, Nguyen, Bich-Yen, White, Ted
• Granted Patent: US 7,494,856 B2
• Time in Patent Office: Days
• US Class Current: 438/262
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH₄OH:H₂O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

Claims

1. A semiconductor fabrication process comprising:

forming an integrated circuit wafer including an active semiconductor layer overlying an etch stop layer (ESL) overlying a buried oxide (BOX) layer;

forming a gate structure, including a gate electrode overlying a gate dielectric, overlying a transistor channel of said active semiconductor layer;

etching source/drain regions deposed on either side of the transistor channel to form source/drain voids, wherein said source/drain voids expose said ESL; and

filling said source/drain voids with source/drain stressors overlying said ESL, wherein a lattice constant of said source/drain stressors differs from a lattice constant of the active semiconductor layer.

2. The semiconductor fabrication process of claim 1, wherein said forming of said integrated circuit wafer includes:

forming said etch stop layer on a semiconductor substrate of a donor wafer;

depositing a dielectric layer on said etch stop layer;

implanting hydrogen into said donor wafer to form a region of damage in said semiconductor substrate of said donor wafer;

depositing a dielectric layer on a semiconductor substrate of a handle wafer; and

bonding the dielectric layer of the donor wafer to the dielectric layer of the handle wafer, and

cleaving said donor wafer along said region of damage.

3. The semiconductor fabrication process of claim 1, wherein forming said active semiconductor layer comprises silicon and wherein said ESL comprises a semiconductor compound.

4. The method in claim 3, wherein said semiconductor compound is pseudomorphic with respect to said active semiconductor layer.

5. The semiconductor fabrication process of claim 4, wherein said semiconductor compound comprises a silicon germanium compound Si_(1-X)Ge_X wherein a percentage of germanium in the silicon germanium compound (X) is in a range of approximately 5 to 15%.

6. The semiconductor fabrication process of claim 5, wherein said source/drain stressor comprises a silicon germanium compound Si_(1-Y)Ge_Y wherein a percentage of germanium (Y) in the silicon germanium compound is higher than X.

7. The semiconductor fabrication process of claim 4, wherein said source/drain stressor comprises a silicon carbon compound.

8. The semiconductor fabrication process of claim 1, wherein forming said integrated circuit wafer includes forming said active semiconductor layer and said ESL wherein an etch selectivity between said active semiconductor layer and said ESL equals or exceeds 10:

1.

9. The semiconductor fabrication process of claim 8, wherein said active semiconductor layer is silicon and wherein said ESL is silicon germanium.

10. The semiconductor fabrication process of claim 9, wherein etching said source/drain regions includes dipping said integrated circuit wafer in a solution of NH₄OH:

H₂O heated to a temperature of approximately 75 C.

11. The semiconductor fabrication process of claim 1, wherein forming the integrated circuit comprises growing said active semiconductor layer over said ESL using epitaxy and wherein filling said source/drain voids comprises growing said source/drain voids using epitaxy.

12. A semiconductor fabrication process, comprising:

forming a silicon germanium etch stop layer (ESL) overlying a buried oxide (BOX) layer of a wafer and an active semiconductor layer overlying the silicon germanium ESL;

forming a gate electrode overlying a transistor channel of the active semiconductor layer;

etching source/drain regions of the active semiconductor layer displaced on either side of the transistor channel to expose the ESL using an etch process; and

forming source/drain stressors on the ESL and displaced on either side of the transistor channel, wherein the source/drain stressors strain the transistor channel.

13. The semiconductor fabrication process of claim 12, wherein forming the layer of silicon germanium ESL comprises growing the ESL epitaxially.

14. The semiconductor fabrication process of claim 12, wherein said silicon germanium ESL is pseudomorphic with said active semiconductor layer.

15. The semiconductor fabrication process of claim 12, wherein a ratio of an etch rate of the active semiconductor layer to an etch rate of the ESL equals or exceeds 10:

1.

16. The semiconductor fabrication process of claim 12, wherein etching said source/regions comprises wet etching said wafer in a solution of NH₄OH:

H₂O heated to a temperature of approximately 75°

C.

17. The semiconductor fabrication process of claim 12, wherein the ESL comprises silicon germanium having a first percentage of germanium and wherein the source/drain stressors are comprised of silicon germanium having a second percentage of germanium, wherein the second percentage differs from the first.

18. The semiconductor fabrication process of claim 17, wherein the second percentage is greater than the first percentage.

19. The semiconductor fabrication process of claim 12, wherein the source/drain stressors are comprised of silicon carbon.

20. A semiconductor fabrication method, comprising:

forming a silicon germanium etch stop layer (ESL) overlying a buried oxide (BOX) layer;

forming source/drain stressors of silicon germanium or silicon carbon overlying the ESL and laterally disposed on either side of a silicon transistor channel; and

forming a gate electrode overlying the transistor channel.