Method of forming sub-100nm narrow trenches in semiconductor substrates

• US 20070238251A1
• Filed: 04/05/2006
• Published: 10/11/2007
• Est. Priority Date: 04/05/2006
• Status: Abandoned Application

• Current Assignee: M-Mos Semiconductor Sdn. Bhd.
• Original Assignee: M-Mos Semiconductor Sdn. Bhd.
• Inventors: Hshieh, Fwu-Iuan, Liew, Patsda Ai, Liau, Chu
• Application Number:
  US11/399,046
• Publication Number:
  US 20070238251A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A method to form a narrow trench within a semiconductor substrate includes exemplary steps of: (a) A CVD layer such as SiO₂ represented as “CVD1” is deposited on top of a semiconductor surface followed by a different type of CVD layer such as SiON or Si₃N₄ (represented by “CVD2” deposited on top of “CVD1”. (b) A 0.2 um trench is formed by partially etching a trench in the CVD deposited layers with a substantial “CVD1” thickness left in order to act as a hard mask layer in the later stage. (c) A thin layer of polysilicon is then deposited in the trench such that the polysilicon covers conformally on the trench wall, trench bottom and on top of the “CVD2” layer. (d) The polysilicon at the trench bottom is then blanket etched to expose the “CVD1” substrate again. (e) The remaining “CVD1” substrate, which is exposed now at the trench bottom, will go through a “CVD1” etching process with good selectivity to Polysilicon and “CVD2” in order to expose the semiconductor substrate at trench bottom. (f) The narrow “CVD1” trench, which is now formed, will go through another etching process to etch the semiconductor substrate with the narrow “CVD1” trench acting as a hard mask. In preferred embodiments, the method of the present invention is used to manufacture trenched MOSFET device.

Claims

1. A method of forming a trench MOSFET comprising:

providing a semiconductor wafer of a first conductivity type;

depositing an epitaxial layer of said first conductivity type over said wafer, said epitaxial layer having a lower majority carrier concentration than said wafer;

forming a body region of a second conductivity type within an upper portion of said epitaxial layer;

providing a first masking material layer over the said epitaxial layer;

said first masking material layer comprises of a densified non-doped silica glass layer;

providing a second masking material layer over the said first masking material layer;

said second masking material layer comprises of silicon oxynitride or silicon nitride layer;

providing the patterned first and second masking material layers;

said patterned first and second masking material layers comprising a densified non-doped silica glass layer and silicon oxynitride layer respectively overlaid by a positive photoresist material, and said patterned masking material layers comprising a first aperture within the first and second masking material layer;

depositing a third masking material layer over said first and second masking material layer, said third masking material layer comprising a doped polysilicon layer;

etching said third masking material layer until a second aperture is created in said second masking material layer within said first aperture, said second aperture being narrower than said first aperture;

etching the remaining stack of first masking material layer within the second aperture until the epitaxial layer is exposed in order to form the third oxide hard mask aperture;

forming a trench in said epitaxial layer by etching said semiconductor wafer through said third aperture of which the said second aperture formed by polysilicon spacer will be removed too; and

removing the first and second masking material layer prior to performing the following steps;

forming an insulating layer lining at least a portion of said trench;

forming a conductive region within said trench adjacent said insulating layer; and

forming a source region of said first conductivity type within an upper portion of said body region and adjacent said trench, wherein said step of forming a source region is performed subsequent to said step of forming a trench.

2. The method of claim 1 wherein said patterned first and second masking material layers are provided over said semiconductor wafer by a method comprising:

providing a first masking material layer over said epitaxial layer;

providing a second masking material layer over the said first masking material layer;

applying a patterned photoresist layer over said second masking material layer;

etching said second masking material layer fully through an aperture in said patterned photoresist layer and followed by etching the said second masking material layer to a specified thickness such that said first aperture is formed in said first and second masking material layers.

3. The method of claim 1, wherein said semiconductor wafer is silicon wafer and said epitaxial layer is a silicon epitaxial layer.

4. The method of claim 1, wherein said first and second masking material layers are of the different material composition such that there will be a relatively good etch selectivity of first masking material to the second masking material.

5. The method of claim 1, wherein said first material layer is silicon dioxide layer and second masking material layer is silicon oxynitride layer.

6. The method of claim 1, wherein said process of etching said first and second masking material is an anisotropic process comprising of first a silicon oxynitride dry etching process followed by a silicon dioxide dry etching process.

7. The method of claim 1, wherein said the third masking material is a polysilicon layer (doped or undoped, polycrystalline or amorphous)

8. The method of claim 1, wherein said process of etching the third masking material layer is an anisotropic polysilicon dry etching process.

9. The method of claim 1, wherein said process of etching the remaining stack of first masking material;

i.e. oxide layer is an anisotropic oxide dry etching process with relatively good selectivity to silicon oxynitride.

10. The method of claim 1, wherein said process of etching said semiconductor is an anisotropic, reactive ion etching process.

11. The method of claim 2, wherein said photoresist layer is a positive resist layer.

12. The method of claim 1, wherein said first trench mask aperture ranges from 0.18 to 0.2 microns in smallest dimension and said second trench mask aperture ranges from 0.13 to 0.07 microns in smallest dimension.