SIMPLIFIED PITCH DOUBLING PROCESS FLOW

• US 20070238299A1
• Filed: 05/03/2007
• Published: 10/11/2007
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Alapati, Ramakanth, Zhou, Baosuo, Niroomand, Ardavan
• Granted Patent: US 7,732,343 B2
• Time in Patent Office: Days
• US Class Current: 438/700
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

patterning a layer of photoresist material to form a plurality of mandrels;

using an atomic layer deposition technique to deposit an oxide material onto the plurality of mandrels;

anisotropically etching the oxide material from exposed horizontal surfaces; and

etching the photoresist material selectively with respect to the oxide material, thereby forming a plurality of oxide spacers.

2. The method of claim 1, wherein the oxide material is deposited using a precursor selected from the group consisting of Si₂Cl₆, H₂0 and C₅H₅N.

3. The method of claim 1, wherein:

the plurality of mandrels are formed in a device array region; and

the oxide material is also deposited over a device peripheral region.

4. The method of claim 3, further comprising forming a pattern of photoresist material over the oxide material in the device peripheral region.

5. The method of claim 4, wherein etching the photoresist material selectively further comprises etching photoresist material from the device peripheral region selectively.

6. The method of claim 1, further comprising isotropically etching the plurality of mandrels to form a plurality of modified mandrels before depositing the oxide material.

7. The method of claim 6, wherein isotropically etching the plurality of mandrels comprises using an oxygen-containing plasma selected from the group consisting of a SO₂/O₂/N₂/Ar plasma, a Cl₂/O₂/He plasma, and a HBr/O₂/N₂ plasma.

8. The method of claim 6, wherein the modified mandrels have a width between about 35 nm and about 70 nm.

9. The method of claim 1, wherein patterning the layer of photoresist comprises using nano-imprint lithography.

10. The method of claim 1, wherein anisotropically etching the oxide material comprises using a HBr/Cl₂-containing plasma.

11. The method of claim 1, wherein the oxide material is deposited at a temperature less than about 100°

C.

12. The method of claim 1, wherein the oxide material is deposited at a temperature less than about 80°

C.

13. The method of claim 1, wherein the layer of photoresist material is patterned over a hard mask layer.

14. The method of claim 1, wherein the layer of photoresist material is patterned over a silicon oxynitride layer that is positioned over a carbon layer.

15. The method of claim 1, wherein the plurality of mandrels have a height between about 50 nm and about 300 nm.

16. The method of claim 1, wherein the layer of photoresist material comprises a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.

17. A method of forming a memory device, the method comprising:

forming a plurality of mandrels over a substrate, the mandrels separated by exposed portions of the substrate;

depositing a spacer material over the mandrels and over the exposed portions of the substrate using an atomic layer deposition technique conducted at a temperature less than about 100°

C.; and

anisotropically etching the spacer material from (a) exposed horizontal surfaces of the plurality of mandrels and (b) the exposed portions of the substrate, thereby leaving spacer material remaining on vertical sidewalls of the plurality of mandrels.

18. The method of claim 17, wherein the substrate includes a hard mask directly under the spacer material.

19. The method of claim 17, further comprising removing the plurality of mandrels, thereby leaving a pattern of spacers positioned over the substrate.

20. The method of claim 19, wherein the spacers comprising the pattern of spacers have a width of about 50 nm or less.

21. The method of claim 19, wherein the spacer material is deposited to a thickness x over the mandrels, and wherein the spacers comprising the pattern of spacers comprising the pattern of spacers have a width x.

22. The method of claim 19, further comprising transferring the pattern of spacers into an amorphous carbon hard mask.

23. A method of forming an integrated circuit, the method comprising:

forming a plurality of mandrels on a hard mask layer, wherein the mandrels comprise a photosensitive material;

depositing a spacer material using an atomic layer deposition technique, wherein the spacer material covers the plurality of mandrels;

anisotropically etching the spacer material from horizontal surfaces, thereby exposing photosensitive material;

removing exposed photosensitive material after anisotropically etching the spacer material, thereby leaving a pattern of spacers on the hard mask layer;

transferring the pattern of spacers to the hard mask layer; and

etching the pattern of spacers from the hard mask layer.

24. The method of claim 23, wherein the hard mask layer comprises carbon.

25. The method of claim 23, wherein:

the mandrels are formed in an array region of the integrated circuit;

and

the spacer material is deposited over (a) the array region of the integrated circuit and (b) a peripheral region of the integrated circuit, the peripheral region surrounding the array region.

26. The method of claim 25, further comprising:

forming a pattern of photosensitive material over the spacer material in the peripheral region before anisotropically etching; and

removing exposed photosensitive material from the peripheral region after anisotropically etching the spacer material.

27. The method of claim 23, wherein the hard mask layer comprises carbon and a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.

28. The method of claim 23, wherein the hard mask layer is positioned over a semiconductor substrate.

29. The method of claim 23, wherein the spacer material is deposited at a temperature less than about 100°

C.

30. The method of claim 23, further comprising isotropically etching the plurality of mandrels before depositing the spacer material.

31. A method of integrated circuit fabrication, the method comprising:

using a lithographic technique to define a plurality of elongate mandrels over a hard mask layer, wherein the mandrels comprise a photoresist material; and

forming a pattern of spacers around the mandrels, wherein;

the pattern of spacers has a pitch that is smaller than a minimum resolvable pitch of the lithographic technique,

the pattern of spacers is formed from an oxide material, and

the pattern of spacers is deposited using an atomic layer deposition technique at a temperature less than about 100°

C.

32. The method of claim 31, wherein the pattern of spacers is deposited at a temperature less than about 80°

C.

33. The method of claim 31, wherein the pattern of spacers is deposited at a temperature less than about 30°

C.

34. The method of claim 31, further comprising transferring the pattern of spacers into the hard mask layer.

35. The method of claim 34, wherein transferring the pattern of spacers into the hard mask layer further comprises exposing a portion of a substrate that underlies the hard mask layer.

36. The method of claim 31, wherein the pattern of spacers comprises a pattern of spacer loops formed around the mandrels.

37. The method of claim 31, wherein the hard mask layer comprises a material selected from the group consisting of silicon, silicon nitride and silicon oxynitride.

38. The method of claim 31, wherein the hard mask layer comprises a dielectric antireflective coating.

39. The method of claim 31, wherein the hard mask layer comprises an organic antireflective coating.

40. The method of claim 31, wherein the hard mask layer is formed over a semiconductor substrate.

41. The method of claim 31, wherein the hard mask layer is formed over a semiconductor substrate and an amorphous carbon layer.

42. The method of claim 31, wherein the mandrels have a height between about 50 nm and about 300 nm.

43. The method of claim 31, wherein the mandrels have a height between about 200 nm and about 250 nm.

44. The method of claim 31, wherein the mandrels comprise a material selected from the group consisting of amorphous carbon, argon fluoride photoresist, and krypton fluoride photoresist.

45. The method of claim 31, wherein the pattern of spacers has a pitch between about 70 nm and about 120 nm.

46. The method of claim 31, wherein the patterns has a pitch between about 80 nm and about 100 nm.