METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20070238321A1
• Filed: 04/10/2007
• Published: 10/11/2007
• Est. Priority Date: 04/10/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Suzuki, Hidenori, Futase, Takuya, Kimoto, Mitsuo, Tsugane, Hideaki
• Granted Patent: US 7,566,662 B2
• Time in Patent Office: Days
• US Class Current: 438/502
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/67167 surrounding a central transfer chamber
• CPC Class Codes: H01L 21/67184 characterized by the presence of more than one transfer chamber
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 438/906 Cleaning of wafer as interim step

Abstract

Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.

Claims

1. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage;

(c) heat treating the semiconductor wafer at a first temperature which has utilized a heating temperature of the shower head;

(d) transferring the semiconductor wafer from the first chamber to a second chamber; and

(e) heat treating the semiconductor wafer in the second chamber at a second temperature greater than the first temperature.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the first temperature is from 100 to 150°

C.

3. A method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is from 150 to 400°

C.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is from 165 to 350°

C.

5. A method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is from 180 to 220°

C.

6. A method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is 200°

C.

7. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer is vacuum-transferred between the first chamber and the second chamber.

22. A method of manufacturing a semiconductor device according to claim 1, wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.

8. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage; and

(c) heat treating the semiconductor wafer at a first temperature which has utilized the heating temperature of the shower head,

wherein the shower head is maintained at a temperature greater than 180°

C.

9. A method of manufacturing a semiconductor device according to claim 8, wherein the first temperature is from 180 to 220°

C.

10. A method of manufacturing a semiconductor device according to claim 8, wherein the first temperature is 200°

C.

21. A method of manufacturing a semiconductor device according to claim 8, wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.

11. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage;

(c) transferring the semiconductor wafer from the first chamber to the second chamber; and

(d) heat treating the semiconductor wafer at a second temperature in the second chamber,

wherein in the step (b), no reducing gas is supplied to the side surface and back surface of the semiconductor wafer.

12. A method of manufacturing a semiconductor device according to claim 11, wherein the second temperature is from 150 to 400°

C.

13. A method of manufacturing a semiconductor device according to claim 11, wherein the second temperature is from 165 to 350°

C.

14. A method of manufacturing a semiconductor device according to claim 11, wherein the second temperature is from 180 to 220°

C.

15. A method of manufacturing a semiconductor device according to claim 11, wherein the second temperature is from 200°

C.

16. A method of manufacturing a semiconductor device according to claim 11, wherein the step (b) comprises a sub-step of:

(b1) holding down, with a sealing, the peripheral portion of the semiconductor wafer placed over the wafer stage.

17. A method of manufacturing a semiconductor device according to claim 11, wherein the step (b) comprises the sub-steps of:

(b1) adsorbing the semiconductor wafer onto the wafer stage by using an electrostatic chuck; and

(b2) covering the peripheral portion of the semiconductor wafer with a shadow ring without bringing the ring into contact with the semiconductor wafer and supplying an inert gas from the peripheral portion of the wafer stage.

18. A method of manufacturing a semiconductor device according to claim 11, wherein the step (b) comprises the sub-steps of:

(b1) holding down, with a sealing, the peripheral portion of the semiconductor wafer placed over the wafer stage; and

(b2) supplying an inert gas from the back side of the wafer stage.

19. A method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor wafer is vacuum-transferred from the first chamber to the second chamber.

20. A method of manufacturing a semiconductor device according to claim 11, wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.