Transactional memory virtualization

• US 20070239942A1
• Filed: 03/30/2006
• Published: 10/11/2007
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rajwar, Ravi, Akkary, Haitham, Lai, Konrad
• Granted Patent: US 8,180,967 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

Claims

1. A processor comprising:

a first logic to store data corresponding to a transactional memory access request in a first portion of a memory in response to an overflow condition caused by the transactional memory request;

a second logic to update a first value in response to the overflow condition.

2. The processor of claim 1, further comprising a third logic to perform one or more operations corresponding to the transactional memory access request in accordance with the stored data.

3. The processor of claim 2, wherein the one or more operations correspond to one or more of a load operation or a store operation.

4. The processor of claim 2, wherein the third logic causes at least some of one or more operations corresponding to the transactional memory access request to be executed speculatively.

5. The processor of claim 1, wherein the first portion of the memory comprises one or more entries corresponding to the transactional memory access request.

6. The processor of claim 5, wherein the one or more entries comprise one or more of a tag field, a data field, a state filed, or a transaction identifier field.

7. The processor of claim 1, further comprising a third logic to restore a state of one or more components of the processor after at least one operation corresponding to the transactional memory access request fails to commit.

8. The processor of claim 7, wherein the third logic restores the state of the one or more components of the processor to one or more of an inner-most, an outer-most, or an intermediate nesting level of the transactional memory access request.

9. The processor of claim 1, further comprising a third logic to abort the transactional memory access when a conflict with a different instruction occurs.

10. The processor of claim 9, wherein the different instruction is an instruction corresponding to a different transactional memory access request.

11. The processor of claim 1, further comprising a third logic to generate a signal to flush one or more corresponding store operations from one or more store buffers after an indication that a first overflow into the first portion of the memory is about to occur.

12. An apparatus comprising:

a counter to count a number of transactional memory access requests that have caused an overflow condition.

13. The apparatus of claim 12, wherein a value of the counter corresponds to a number of existing overflow transactions that have caused an overflow into a first portion of a memory.

14. The apparatus of claim 12, further comprising a first logic to control execution of one or more transactional memory requests in accordance with a value of the counter.

15. The apparatus of claim 12, further comprising one or more processor cores to perform one or more operations corresponding to one or more of the transactional memory access requests.

16. The apparatus of claim 15, wherein the one or more processor cores and the counter are on a same die.

17. The apparatus of claim 12, further comprising a cache to store data corresponding to one or more of the transactional memory access requests, wherein the cache comprises one or more bits to indicate an access corresponding to the one or more transactional memory access requests to a portion of the cache.

18. The apparatus of claim 17, further comprising a first logic to access the one or more bits to determine a previous access to the portion of the cache.

19. The apparatus of claim 17, wherein the portion of the cache is one or more of a cache line or a cache block.

20. The apparatus of claim 17, wherein the cache comprises one or more of a mid-level cache (MLC) or a last-level cache (LLC).

21. A method comprising:

storing data corresponding to a transactional memory instruction that has caused a hardware overflow into a persistent portion of a memory;

updating a stored value corresponding to a number of transactional memory access requests that are uncommitted in response to at least the first instruction; and

performing one or more operations in response to the first instruction in accordance with the stored data.

22. The method of claim 21, further comprising generating a signal to flush one or more corresponding store operations from one or more store buffers after an indication that a first overflow into the persistent portion of the memory is about to occur.

23. The method of claim 21, further comprising restoring a state of one or more components of a processor after at least one of the one or more operations fails to commit.

24. The method of claim 21, further comprising determining whether the hardware overflow corresponds to a cache overflow or a cache miss.

25. A system comprising:

a first memory to store data;

a processor to fetch a first instruction corresponding to a start of a transactional memory access and a second instruction corresponding to an end of the transactional memory access, the processor to store data corresponding to a transactional memory access request that has caused a second memory to overflow in the first memory and to update a value stored in a storage unit in response to performing one or more of the first instruction and the second instruction.

26. The system of claim 25, further comprising a fourth logic to restore a state of one or more components of the processor after at least one of one or more operations corresponding to the transactional memory access fails to commit.

27. The system of claim 25, further comprising a fourth logic to generate a signal to flush one or more corresponding store operations from one or more store buffers after an indication that a first overflow into the first memory is about to occur.

28. The system of claim 25, further comprising an audio device.

29. A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to:

store data corresponding to a transactional memory instruction that has caused a hardware overflow into a persistent portion of a memory;

update a stored value corresponding to a number of transactional memory access requests that are uncommitted in response to the transactional memory instruction, and

restore a state of one or more components of a processor core after at least one operation corresponding to the transactional memory instruction fails to commit.

30. The computer-readable medium of claim 29, further comprising one or more instructions that configure the processor to execute one or more operations corresponding to a user handler in response to the transactional memory instruction.

31. The computer-readable medium of claim 29, further comprising one or more instructions that configure the processor to determine whether the hardware overflow corresponds to a cache overflow or a cache miss.