Asynchronously-accessible memory devices and access methods

• US 20070239956A1
• Filed: 05/24/2007
• Published: 10/11/2007
• Est. Priority Date: 01/11/1996
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd, Williams, Brett, Ryan, Kevin, Mailloux, Jeffrey
• Application Number:
  US11/805,884
• Publication Number:
  US 20070239956A1
• Time in Patent Office: Days
• US Class Current: 711/169
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Apparatus and methods may operate to switch between burst modes and pipelined modes without using a WCBR (write and column address select before row address select) cycle, as well as to select an external address data path, instruct a memory to perform a desired memory operation, and perform the desired memory operation until terminated.

Claims

1. A method of accessing an asynchronous memory, including:

switching between a burst extended data out (EDO) mode and a pipelined EDO mode without using a WCBR (write and column address select before row address select) cycle;

selecting an external address data path;

instructing the asynchronous memory to perform a desired memory operation; and

performing the desired memory operation until terminated.

2. The method of claim 1, wherein the selecting includes selecting the external address data path from a buffer when the switching switches to the burst EDO mode.

3. The method of claim 1, wherein the desired memory operation is selected from a group consisting of a read operation and a write operation.

4. The method of claim 1, wherein the performing includes obtaining an external column address to perform the desired memory operation.

5. The method of claim 4, wherein the performing includes iterating the obtaining until terminated.

6. The method of claim 1, wherein the performing includes generating an internal column address to perform the desired memory operation.

7. The method of claim 6, wherein the generating includes iterating the generating until terminated.

8. The method of claim 1, further including:

obtaining a first external column address; and

accessing the asynchronous memory when the switching switches to the pipeline EDO mode.

9. The method of claim 8, further including:

obtaining a second external column address subsequent to receiving the first external column address during operation in the pipelined EDO mode.

10. The method of claim 1, further including:

generating an internal column address subsequent to receiving an external column address during operation in the burst EDO mode, the internal column address patterned after the external column address.

11. The method of claim 1, further including:

selecting an internal address pathway based on the switching between the burst EDO mode and the pipelined EDO mode.

12. The method of claim 1, wherein the selecting further including:

selecting an initial buffered external address data path;

obtaining an initial external column address;

accessing the asynchronous memory; and

generating internal column addresses when the switching switches to the burst EDO mode.

13. An asynchronous memory device, including:

mode selection circuitry configured to select between a burst extended data out (EDO) mode and a pipelined EDO mode;

an external column address data path to operate during pipelined EDO mode operations;

an internal column address generation module to operate during burst EDO mode operations; and

pipelined/burst circuitry to couple to the mode selection circuitry and to switch between the pipelined EDO mode and the burst EDO mode without using a WCBR (write and column address select before row address select) cycle.

14. The asynchronous memory device of claim 13, further including:

selection circuitry for selecting between a read operation and a write operation.

15. The asynchronous memory device of claim 13, wherein the pipelined EDO mode operations include read and write operation column address retrieval.

16. The asynchronous memory device of claim 13, wherein the burst EDO mode operations include read and write operation column address generation.

17. The asynchronous memory device of claim 13, further including:

an external mode selection pin coupled to the mode selection circuitry.

18. The asynchronous memory device of claim 13, further including:

asynchronous dynamic random access memory cells to couple to the internal column address generation module.

19. The asynchronous memory device of claim 13, wherein the pipelined/burst circuitry includes a buffer to store an address.

20. The asynchronous memory device of claim 19, wherein the pipelined/burst circuitry includes at least one counter to increment the address.