Processing apparatus

• US 20070240083A1
• Filed: 03/26/2007
• Published: 10/11/2007
• Est. Priority Date: 03/28/2006
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Hiroi, Toshiyuki, Sugawara, Akihiko
• Granted Patent: US 8,134,226 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a processing apparatus, a plurality of processors which perform different kinds of processing is integrated on a first semiconductor substrate. A plurality of memories to be managed by the plurality of processors integrated on the first semiconductor substrate is integrated on a second semiconductor substrate. The plurality of processors integrated on the first semiconductor substrate includes respective separate memory controllers which control the memories to be managed that are integrated on the second semiconductor substrate. The semiconductor substrates are manufactured using different semiconductor manufacturing processes, and micro bumps are formed on their respective surfaces. The semiconductor substrates are stacked together in the thickness direction, and are connected to each other through the micro bumps.

Claims

1. A processing apparatus comprising:

a first semiconductor substrate on which a plurality of processors for performing different processing is integrated; and

a second semiconductor substrate on which a plurality of memories to be respectively managed by the plurality of processors integrated on the first semiconductor substrate is integrated, wherein

the plurality of processors integrated on the first semiconductor substrate includes respective separate memory controllers for controlling the memories to be managed that are integrated on the second semiconductor substrate.

2. The processing apparatus according to claim 1, wherein:

the first and second semiconductor substrates are manufactured using different semiconductor manufacturing processes;

micro bumps are formed on the respective surfaces thereof; and

the first and second semiconductor substrates are stacked together in a thickness direction, and connected to each other through the micro bumps.

3. The processing apparatus according to claim 2, wherein the plurality of processors and the respective plurality of memories to be managed are arranged so that the respective projections thereof at least partially overlap each other.

4. A processing apparatus comprising:

an arithmetic processor which performs general-purpose processing;

a memory to be managed by the arithmetic processor;

a plurality of application-specific processors which are designed to perform specific processing; and

application-specific memories to be managed by the plurality of application-specific processors,

wherein the arithmetic processor and the application-specific processors excluding an image processor for performing image processing are integrated on a first semiconductor substrate, and

wherein the memory to be managed by the arithmetic processor and the application-specific memories to be managed by the application-specific processors excluding the image processor are integrated on a second semiconductor substrate.

5. The processing apparatus according to claim 4, wherein the image processor and the memory to be managed by the image processor are integrated on a third semiconductor substrate.

6. The processing apparatus according to claim 4, wherein the first and second semiconductor substrates are manufactured using different semiconductor manufacturing processes, respectively.

7. A processing apparatus comprising:

a plurality of processors; and

a plurality of memories to be managed by the plurality of processors, wherein

the plurality of processors and the plurality of memories are classified depending on respective semiconductor manufacturing processes optimal for manufacturing these, and processors and memories classified for an identical semiconductor manufacturing process are formed on the same semiconductor substrate.