Method and system for optimizing performance based on cache analysis

• US 20070240117A1
• Filed: 02/22/2006
• Published: 10/11/2007
• Est. Priority Date: 02/22/2006
• Status: Active Grant

• Current Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Original Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Inventors: Koning, Maarten, Wiles, Roger
• Granted Patent: US 8,266,605 B2
• Time in Patent Office: Days
• US Class Current: 717/124
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862

Abstract

Described is a method and system for optimizing a code layout for execution on a processor including internal and/or external cache memory. The method and system includes executing a program having a first layout, generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run and constructing a second layout for the program as a function of the at least one memory access parameter.

Claims

1. A method, comprising:

executing a program having a first layout;

generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run; and

constructing a second layout for the program as a function of the at least one memory access parameter.

2. The method according to claim 1, wherein the at least one memory access parameter is one of cache access data and execution path data.

3. The method according to claim 1, wherein the layout is one of a code layout and a data layout.

4. The method according to claim 1, wherein the generating the at least one memory access parameter includes:

analyzing accesses to the cache memory.

5. The method according to claim 1, wherein the method is performed on a second computing system.

6. The method according to claim 5, wherein the second computing system is a hardware simulator with instruction execution capabilities.

7. The method according to claim 1, wherein the generating the at least one memory access parameter includes:

counting a number of times a preselected path in the program is executed.

8. The method according to claim 6, further comprising:

identifying cache lines hit for the preselected path.

9. The method according to claim 1, wherein the at least one memory access parameter includes at least one of (i) cache hits, (ii) cache misses, (iii) cache collisions, (iv) contention for a predetermined cache line, (v) a processing time for a predetermined portion of the program (vi) a location in the program of a processor at a predetermined interval and (vii) a manually tagged portion of the program.

10. The method according to claim 1, further comprising:

generating at least one further memory access parameter for the program in the second layout; and

comparing the at least one further memory access parameter to a predetermined threshold.

12. The system according to claim 10, wherein the simulator analyzes accesses to the cache memory as the program is executing.

13. The system according to claim 10, wherein the simulator counts a number of times a preselected path in the program is executed.

14. The system according to claim 12, wherein the simulator identifies cache lines hit for the preselected path.

15. The system according to claim 10, wherein the at least one memory access parameter includes at least one of (i) cache hits, (ii) cache misses, (iii) cache collisions, (iv) contention for a predetermined cache line, (v) a processing time for a predetermined portion of the program (vi) a location in the program of a processor at a predetermined interval and (vii) a manually tagged portion of the program.

16. The system according to claim 10, wherein the simulator generates at least one further memory access parameter for the program in the second layout and compares the at least one further memory access parameter to a predetermined threshold.

17. The system according to claim 15, wherein the predetermined threshold is an optimal cache usage profile.

18. The system according to claim 10, wherein the computing system on which the program is designed to run includes the cache memory and a main memory, wherein the second code layout has less cache line contentions than the first code layout.

19. The system according to claim 10, wherein the computing system on which the program is designed to run includes the cache memory and a main memory, wherein the second code layout has less cache collisions than the first code layout.

11. A system, comprising:

a simulator to execute a program having a first layout, the simulator generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run; and

a linker to construct a second layout for the program as a function of the at least one memory access parameter.

20. A system including a memory to store a set of instructions and a processor to execute the set of instructions, the set of instructions being operable to:

execute a program having a first layout;

generate at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run; and

construct a second layout for the program as a function of the at least one memory access parameter.