Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts

• US 20070241378A1
• Filed: 04/13/2006
• Published: 10/18/2007
• Est. Priority Date: 04/13/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,638,878 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.

Claims

1. A semiconductor device having a cross section comprising:

a semiconductor wafer;

a first bit line, wherein the first bit line has an upper surface and a lower surface, with the upper surface being more outwardly located on the semiconductor wafer than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located on the semiconductor wafer than the lower surface, and wherein the upper surface of the second bit line is more outwardly located on the semiconductor wafer than the upper surface of the first bit line and the first bit line is adjacent to the second bit line.

2. The semiconductor device of claim 1, wherein the lower surface of the second bit line is more outwardly located on the semiconductor wafer than the lower surface of the first bit line.

3. The semiconductor device of claim 1, wherein the lower surface of the second bit line is at about the elevation with respect to the semiconductor wafer as the lower surface of the first bit line.

4. The semiconductor device of claim 1, wherein the lower surface of the second bit line is more outwardly located on the semiconductor wafer than the upper surface of the first bit line.

5. The semiconductor device of claim 1 further comprising:

at least two first bit lines;

a second bit line contact electrically coupled to the second bit line and to the semiconductor wafer,

wherein the second bit line contact is interposed directly between the two first bit lines.

6. A semiconductor device comprising:

a first cross-sectional location, comprising;

a plurality of first and second doped regions within a semiconductor wafer;

a first plurality of bit line plugs contacting the first doped regions, wherein no bit line plug contacts any of the second doped regions at the first cross-sectional location;

a plurality of first bit lines contacting the plurality of bit line plugs; and

a plurality of second bit lines, wherein a lower surface of the second bit lines is above an upper surface of the first bit lines;

a second cross-sectional location comprising;

a plurality of first and second doped regions within a semiconductor wafer;

a second plurality of bit line plugs contacting the second doped regions, wherein no bit line plug contacts any of the first doped regions at the second cross-sectional location;

the plurality of first bit lines being continuous from the plurality of first bit lines at the first cross-sectional location; and

a plurality of second bit lines contacting the plurality of bit line plugs at the second cross-sectional location, wherein an upper surface of the second bit lines is above an upper surface of the first bit lines.

7. The semiconductor device of claim 6 wherein each of the plurality of second bit lines at the second cross-sectional location comprises:

a first conductive feature interposed between adjacent first bit lines; and

a second conductive feature electrically coupled to one of the second plurality of bit line plugs through the first conductive feature, wherein a lower surface of the second conductive feature at the second cross-sectional location is above an upper surface of the first bit line plugs.

8. The semiconductor device of claim 6 wherein each of the plurality of second bit lines at the second cross-sectional location comprises a single conductive layer which extends from between adjacent first bit lines to a level above an upper level of the first bit lines.

9. The semiconductor device of claim 8 further comprising a conductive enhancement layer interposed between the single conductive layer and the second bit line plug, wherein each second bit line is electrically coupled to one of the second bit line plugs through the enhancement layer.

10. The semiconductor device of claim 6, wherein the plurality of first bit line plugs and the plurality of second bit line plugs each comprise:

a first plug portion comprising a first conductive layer which contacts one of the doped regions within the semiconductor wafer; and

a second plug portion comprising a second conductive layer which contacts the first plug portion and is electrically coupled to the doped region through the first plug portion,

wherein a bit line is electrically coupled to the doped region through the second plug portion and the first plug portion.

11. The semiconductor device of claim 6 further comprising a source local interconnected comprising a conductive layer which also provides the first and second plurality of bit line plugs.

12. The semiconductor device of claim 6 wherein a portion of each bit line of the plurality of second bit lines overlies at least one of the plurality of first bit lines.

13. A semiconductor device, comprising:

a semiconductor wafer substrate assembly comprising a semiconductor wafer;

first bit line plugs at a first cross-sectional location and second bit line plugs at a second cross-sectional location;

a plurality of first bit lines at both the first and second cross-sectional locations, wherein the first bit lines contact the first bit line plugs at the first cross-sectional location but do not contact the second bit line plugs at the second cross-sectional location;

a plurality of second bit lines at both the first and second cross-sectional locations, wherein the second bit lines contact the second bit line plugs at the second cross-sectional location but do not contact the first bit line plugs at the first locations, wherein an upper surface of the second bit lines is more outwardly located on the semiconductor wafer than an upper surface of the first bit lines.

14. The semiconductor device of claim 13 wherein a bottom surface of the second bit lines at the first cross-sectional location is more outwardly located than an upper surface of the first bit lines at the first cross-sectional location.

15. The semiconductor device of claim 13 wherein at least one second bit line is interposed between two adjacent first bit lines at the second cross-sectional location, but the at least one second bit line is not interposed between the two adjacent first bit lines at the first cross-sectional location.

16. The semiconductor device of claim 13 further comprising:

the second bit lines comprising;

a first conductive layer which contacts the second bit line plugs;

a second conductive layer which contact the first conductive layer,

wherein a bottom surface of the second conductive layer at the first cross-sectional location is more outwardly located on the semiconductor wafer than an upper surface of the first bit lines.

17. A method for use during fabrication of a semiconductor device, comprising:

forming a plurality of conductive bit line plugs at a first cross-sectional location and at a second cross-sectional location;

forming a first blanket conductive bit line layer which contacts the plurality of conductive bit line plugs at the first and second cross-sectional locations; and

removing a portion of the first blanket conductive bit line layer to form a plurality of first bit lines which contact the bit line plugs at the first location, but which is removed from contact with the bit line plugs at the second location.

18. The method of claim 17 further comprising:

forming a second blanket conductive bit line layer over the first bit lines and which contacts the bit line plugs at the second location; and

removing a portion of the second blanket conductive bit line layer to form a plurality of second bit line portions which contact the bit line plugs at the second location, but which do not contact the bit line plugs at the first location.

19. The method of claim 18 further comprising planarizing the second blanket conductive bit line layer to remove the second blanket conductive bit line layer from over the plurality of first bit lines to form the second bit line portions.

20. The method of claim 18 further comprising:

forming a third blanket conductive bit line layer over the first bit lines which are electrically coupled to the bit line plugs at the second location through electrical contact with the second bit line portions; and

removing the third blanket conductive bit line layer from over the first bit lines.

21. The method of claim 20 wherein a bottom surface of the third blanket conductive layer at the first cross-sectional location is above a top surface of the first bit lines.

22. The method of claim 18 further comprising:

forming a third blanket conductive bit line layer over the first bit lines which are electrically coupled to the bit line plugs at the second location through electrical contact with the second bit line portions; and

removing a first portion of the third blanket conductive layer from over the first bit lines and leaving a second portion of the third blanket conductive layer over the first bit lines.

23. A method for use during fabrication of a semiconductor device, comprising:

providing a semiconductor wafer substrate assembly comprising a plurality of conductive regions;

providing a plurality of conductive plugs within a first dielectric layer at a first cross-sectional location and at a second cross-sectional location,

wherein each conductive plug electrically contacts one of the conductive regions;

forming a first blanket conductive layer to electrically contact each of the conductive plugs at both the first cross-sectional location and the second cross-sectional location;

forming a blanket second dielectric layer over the blanket conductive layer;

etching the blanket second dielectric layer and the blanket conductive layer to form a plurality of first conductive lines from the first blanket conductive layer, wherein subsequent to the etch a conductive line contacts each of the conductive plugs at the first cross-sectional location, but no portion of the first blanket conductive layer contacts any of the conductive plugs at the second cross-sectional location;

providing a mask layer interposed between adjacent first conductive lines at the first cross-sectional location, wherein the mask layer leaves the conductive plugs at the second cross-sectional location exposed;

forming a second blanket conductive layer over the mask layer at the first cross-sectional location which contacts the conductive plugs at the second cross-sectional location;

planarizing the second blanket conductive layer to remove the second blanket conductive layer from over the mask layer at the first cross-sectional location and to leave the second conductive layer contacting the conductive plugs at the second cross-sectional location; and

forming a plurality of second conductive lines to contact the second conductive layer at the second cross-sectional location, wherein a bottom surface of the second conductive lines at the first cross sectional location is above a top surface of the first conductive lines.

24. The method of claim 23 wherein subsequent to etching the blanket second dielectric layer, both the first cross-sectional location and the second cross-sectional location comprise at least one first conductive line.

25. The method of claim 23 wherein the providing of the mask layer further comprises:

forming a blanket third dielectric layer over the plurality of first conductive lines, over the conductive plugs at the first cross-sectional location, and over the conductive plugs at the second cross-sectional location;

planarizing the blanket third dielectric layer such that a portion of the third dielectric layer remains between the adjacent first conductive lines at both the first cross-sectional location and at the second cross-sectional location;

forming a patterned photoresist layer over the first conductive lines and over the conductive plugs at the first cross-sectional location, but which leaves the third dielectric layer, the conductive plugs, and at least one first conductive line at the second cross-sectional location uncovered by the patterned photoresist layer; and

etching the third dielectric layer at the second cross-sectional location to expose the conductive plugs at the second cross-sectional location, while the third dielectric layer at the first cross-sectional location remains over the first conductive lines and over the conductive plugs at the first cross-sectional location.

26. The method of claim 25 further comprising forming a plurality of spacers along first and second sidewalls of the first conductive lines such that an edge of each spacer is substantially aligned with an edge of one of the contact plugs at the second cross-sectional location.

27. The method of claim 23 further comprising forming a portion of each second conductive line over a portion of at least one of the first conductive lines.

28. A method for use during fabrication of a semiconductor device, comprising:

forming a plurality of conductive bit line plugs at a first cross-sectional location and at a second cross-sectional location;

forming a first blanket conductive bit line layer which contacts the plurality of conductive bit line plugs at the first and second cross-sectional locations; and

removing a portion of the first blanket conductive bit line layer to form a plurality of first bit lines which contact the bit line plugs at the first location, but which is removed from contact with the bit line plugs at the second location;

forming a dielectric layer over the plurality of first bit lines and bit line plugs at the first cross-sectional location, and over the first bit lines and bit line plugs at the second cross-sectional location;

forming a patterned mask over the bit line plugs at the first cross-sectional location and over the first bit lines at both the first and second cross-sectional locations, wherein the bit line plugs at the second location is uncovered by the patterned mask;

etching the dielectric layer using the patterned mask as a pattern to form a plurality of openings in the first dielectric layer which expose the bit line contacts at the second location;

forming a second conductive bit line layer over both the dielectric layer and over the first bit line layer at the first and second cross-sectional locations, and within the plurality of openings in the first dielectric layer to contact the bit line plugs at the second cross-sectional location, wherein the second conductive bit line layer does not contact the bit line plugs at the first cross-sectional location; and

etching the second conductive bit line layer at the first and second cross-sectional locations to form a plurality of second bit lines, wherein at least a portion of the second conductive bit line layer remains within the plurality of openings at the second cross-sectional location and over the dielectric layer at the first cross-sectional location subsequent to the etching of the second conductive bit line layer.

29. The method of claim 28 further comprising:

forming the second conductive bit line layer on the dielectric layer at both the first and second cross-sectional locations;

planarizing the second conductive bit line layer; and

subsequent to planarizing the second conductive bit line layer, performing the etch of the second conductive bit line layer, wherein subsequent to the etch an upper surface of the second conductive bit line layer at both the first and second cross-sectional locations is above an upper surface of the dielectric layer at the first and second cross-sectional locations.

30. The method of claim 28 further comprising performing the etch of the second conductive bit line layer such that subsequent to the etch a lower surface of the second bit lines at the first cross-sectional location is above an upper surface of the first bit lines at the first cross-sectional location.

31. A semiconductor device memory array, comprising:

a first conductive bit line comprising at least one first conductive layer electrically coupled with a first plurality of memory cells; and

a second conductive bit line adjacent to the first bit line comprising at least one second conductive layer and electrically coupled with a second plurality of memory cells, wherein the at least one second conductive layer is a different layer than the at least one first conductive layer.

32. The memory array of claim 31, wherein the first bit line comprises a select gate and the second bit line comprises a memory gate for a nonvolatile memory device.

33. The memory array of claim 31, wherein the memory array comprises a portion of a NAND memory device.

34. The memory array of claim 31 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section and provides at least a portion of a select gate; and

at least a second bit line contact plug which electrically couples the second conductive bit line to a second conductively doped region in the semiconductor wafer section and provides at least a portion of a memory gate.

35. The memory array of claim 34 wherein the first and second bit line contact plugs comprise a staggered arrangement.

36. An electronic device comprising:

at least one semiconductor device having a cross section comprising;

a semiconductor wafer;

a first bit line, wherein the first bit line has an upper surface and a lower surface, with the upper surface being more outwardly located on the semiconductor wafer than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located on the semiconductor wafer than the lower surface,

wherein at least 80% of the length of the upper surface of the second bit line is more outwardly located on the semiconductor wafer than 80% of the upper surface of the first bit line and the first bit line is adjacent to the second bit line.

37. The electronic device of claim 36 wherein the at least one semiconductor device is a nonvolatile memory device, and the electronic device further comprises:

at least one microprocessor in electrical communication with the nonvolatile memory device.

38. A semiconductor device memory array, comprising:

a first bit line comprising a first conductive layer and electrically coupled with a first plurality of memory cells; and

a second bit line comprising a second conductive layer different from the first conductive layer and electrically coupled with a second plurality of memory cells,

wherein the first bit line is adjacent to the second bit line.

39. The semiconductor device memory array of claim 38 wherein the first plurality of memory cells comprises memory at least one select transistor.

40. The semiconductor device memory array of claim 38 wherein the memory array comprises a portion of a NAND memory device.

41. The semiconductor device memory array of claim 38 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section; and

at least a second bit line contact plug which electrically couples the second conductive bit line to a second conductively doped region in the semiconductor wafer section.

42. The semiconductor device memory array of claim 41 wherein the first and second bit line contact plugs comprise a staggered arrangement.

43. A memory array comprising:

a first conductive layer comprising a first bit line electrically coupled with a first plurality of memory cells; and

a second conductive layer comprising a second bit line electrically coupled with a second plurality of memory cells,

wherein the first bit line is adjacent to the second bit line.

44. The memory array of claim 43 wherein the first plurality of memory cells comprises memory at least one select transistor.

45. The memory array of claim 43 further comprising a portion of a NAND memory device.

46. The memory array of claim 43 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section; and

at least a second bit line contact plug which electrically couples the second conductive bit line to a second conductively doped region in the semiconductor wafer section.

47. The memory array of claim 46 wherein the first and second bit line contact plugs comprise a staggered arrangement.