Semiconductor device and method of fabricating the same

• US 20070241399A1
• Filed: 02/13/2007
• Published: 10/18/2007
• Est. Priority Date: 02/15/2006
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takagi, Shinichi, Sugiyama, Naoharu, Irisawa, Toshifumi, Numata, Toshinori
• Granted Patent: US 7,622,773 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Claims

1. A semiconductor device comprising:

a semiconductor layer formed an island shape along a given direction on an insulating film and having a plurality of side surfaces along the given direction, all angles formed by adjacent ones of the side surfaces being larger than 90°

, and a section of the semiconductor layer perpendicular to the given direction being vertically and horizontally symmetrical;

a gate insulating film formed on a region on the side surfaces, which is to be used as a channel;

a gate electrode formed on the gate insulating film; and

source and drain electrodes formed in contact with the semiconductor layer with the gate electrode being arranged between the source and drain electrodes.

2. A device according to claim 1, wherein the gate insulating film and the gate electrode are formed on all the side surfaces so as to surround a portion of the semiconductor layer.

3. A device according to claim 1, wherein the semiconductor layer is made of Ge.

4. A device according to claim 1, wherein the channel of the semiconductor layer is made of Ge, and an extension layer made of a material selected from the group consisting of Si and SiGe is formed between each of the source and drain electrodes and the channel.

5. A device according to claim 1, wherein the channel of the semiconductor layer is made of Ge, and the source and drain electrodes are made of a material selected form the group consisting of germanide, germanosilicide, and silicide, and formed in contact with the channel.

6. A device according to claim 1, wherein the insulating film is formed on a (100) single-crystal semiconductor substrate, and the semiconductor layer is formed along a <

110>

-axis direction of the substrate.

7. A device according to claim 1, wherein four of the side surfaces are (111) surfaces.

8. A device according to claim 1, wherein the section of the semiconductor layer which is perpendicular to the given direction is a hexagon.

9. A device according to claim 1, wherein the gate electrode is formed on the insulating film along a direction intersecting the given direction.

10. A semiconductor device comprising:

a (100) substrate;

a buried insulating film formed on the substrate;

a semiconductor layer formed on the buried insulating film in an island shape along a <

110>

-axis direction of the substrate and having a plurality of side surfaces along the <

110>

-axis direction, all angles formed by adjacent ones of the side surfaces being larger than 90°

, and a section of the semiconductor layer perpendicular to the <

110>

-axis direction being a hexagon which is vertically and horizontally symmetrical;

a gate insulating film formed on a region on the side surfaces, which is to be used as a channel, so as to surround a portion of the semiconductor layer;

a gate electrode formed on the gate insulating film so as to surround a portion of the semiconductor layer; and

source and drain electrodes formed in contact with the semiconductor layer to sandwich the channel of the semiconductor layer which is surrounded by the gate electrode.

11. A device according to claim 10, wherein the gate insulating film and the gate electrode are formed on all the side surfaces along the <

110>

-axis direction so as to surround a portion of the semiconductor layer.

12. A device according to claim 10, wherein the semiconductor layer is made of Ge.

13. A device according to claim 10, wherein the channel of the semiconductor layer is made of Ge, and an extension layer made of a material selected from the group consisting of Si and SiGe is formed between each of the source and drain electrodes and the channel.

14. A device according to claim 10, wherein the channel of the semiconductor layer is made of Ge, and the source and drain electrodes are made of a material selected form the group consisting of germanide, germanosilicide, and silicide, and formed in contact with the channel region.

15. A device according to claim 10, wherein four of the side surfaces along the <

110>

-axis direction of the semiconductor layer are (111) surfaces.

16. A device according to claim 10, wherein the gate electrode is formed on the insulating film along a direction intersecting the <

110>

-axis direction.

17. A method of fabricating a semiconductor device comprising:

forming an SiGe layer on an insulating film;

selectively etching the SiGe layer in an island shape along a given direction in accordance with a MIS transistor formation region, to make an island SiGe layer;

oxidizing the island SiGe layer to form a Ge layer having a plurality of side surfaces along the given direction, all angles formed by adjacent ones of the side surfaces being larger than 90°

, and a section of the Ge layer perpendicular to the given direction being vertically and horizontally symmetrical;

forming a gate insulating film on a region on the side surfaces of the Ge layer, the region being to be used as a channel,;

forming a gate electrode on the gate insulating film; and

forming source and drain electrodes in contact with the Ge layer by using the gate electrode as a mask.

18. A method according to claim 17, wherein the insulating film is formed on a (100) single-crystal semiconductor substrate, and the SiGe layer is etched in an island shape along a <

110>

-axis direction of the substrate.

19. A method according to claim 17, wherein a section of the Ge layer which is perpendicular to the <

110>

-axis direction is a hexagon, and four of the side surfaces along the <

110>

-axis direction of the Ge layer are (111) surfaces.

20. A method according to claim 17, wherein before formation of the source and drain electrodes, an SiGe layer is formed in a region adjacent to the channel by epitaxially growing and annealing a material selected from the group consisting of Si and SiGe by using the gate electrode as a mask.