SEMICONDUCTOR DEVICE

• US 20070241402A1
• Filed: 04/10/2007
• Published: 10/18/2007
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: HIRANO, Yuichi
• Granted Patent: US 7,804,132 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

Claims

1. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, a buried oxide film formed on said semiconductor substrate, and an SOI layer having a first conductivity type formed on said buried oxide film; and

at least one MOS transistor provided on said SOI layer, wherein said at least one MOS transistor comprises;

a first electrode region and a second electrode region having a second conductivity type and selectively provided in the surface of said SOI layer;

a body region having a first conductivity type and corresponding to said SOI layer sandwiched between said first electrode region and said second electrode region;

a gate electrode provided above said body region;

a partial isolation insulation film selectively provided in said SOI layer surface corresponding to the lower part of at least one end of both ends of said gate electrode in a gate width direction, in the peripheral region of an active region comprising said first electrode region, said second electrode region and said body region;

a semiconductor region provided in the surface of said SOI layer so as to be adjacent to said partial isolation insulation film; and

at least one semiconductor region within the electrode region having a first conductivity type, selectively provided in the surface of said first electrode region in the vicinity of said gate electrode and electrically connected to said body region, wherein

said partial isolation insulation film has said SOI layer continued from said body region, in a lower part thereof,

said semiconductor region is in contact with said SOI layer under said partial isolation insulation film, and

a region other than the partial isolation insulation film in the peripheral region of said active region is surrounded by a full isolation insulation film penetrating said SOI layer and reaching said buried oxide film.

2. The semiconductor device according to claim 1, wherein

said partial isolations insulation films are selectively provided in said SOI layer surface corresponding to the lower parts of both ends of said gate electrode in the gate width direction,

said at least one semiconductor region within the electrode region comprises a plurality of semiconductor regions within the electrode region spaced and aligned along said gate electrode, and

said plurality of semiconductor regions within the electrode region are arranged such that the distance between the semiconductor regions within the electrode region, and the distance between the end of the arrangement and the nearest edge of said active region are equal to each other.

3. The semiconductor device according to claim 1, wherein

said partial isolation insulation films are selectively provided in said SOI layer surface corresponding to the lower parts of both ends of said gate electrode in the gate width direction,

said at least one semiconductor region within the electrode region comprises a plurality of semiconductor regions within the electrode region spaced and aligned along said gate electrode, and

said plurality of semiconductor regions within the electrode region are arranged such that a first distance between the end of the arrangement and the nearest edge of the active region is longer than a second distance between the semiconductor regions within the electrode region.

4. The semiconductor device according to claim 3, wherein said first distance is set so as to be the half of the second distance.

5. The semiconductor device according to claim 1, wherein

said partial isolation insulation film is selectively provided in said SOI layer surface corresponding to the lower part of one of both ends of said gate electrode in the gate width direction,

said at least one semiconductor region within the electrode region comprises the plurality of semiconductor regions within the electrode region arranged so as to be spaced along said gate electrode, and

said plurality of semiconductor regions within the electrode region are arranged such that a first distance between the end of the arrangement on the side said partial isolation insulation film is provided and the nearest edge of said active region is longer than a second distance between said semiconductor regions within the electrode region, and a third distance between the end of the arrangement on the opposite side of said partial isolation insulation film and the nearest edge of the active region is shorter than said first distance.

6. The semiconductor device according to claim 1, wherein

said at least one MOS transistor comprises a plurality of MOS transistors in which respective gate electrodes are arranged in parallel in a gate length direction, and

said plurality of MOS transistors are provided so as to share said first electrode region between the adjacent MOS transistors.

7. The semiconductor device according to claim 6, wherein

said semiconductor region within the electrode region provided in said first electrode region shared by said adjacent MOS transistors is provided so as to continuously extend between said gate electrodes.

8. The semiconductor device according to claim 1, wherein

said at least one MOS transistor comprises an N channel MOS transistor in which said first conductivity type is a P type and said second conductivity type is an N type, and a P channel MOS transistor in which said first conductivity type is an N type and said second conductivity type is a P type,

said at least one semiconductor region within the electrode region in said N channel MOS transistor and said P channel MOS transistor comprises a plurality of semiconductor regions within the electrode region arranged so as to be spaced and aligned along said gate electrode, and

the distance between said semiconductor regions within the electrode region in said N channel MOS transistor is set so as to be smaller than the distance between said semiconductor regions within the electrode region in said P channel MOS transistor.

9. The semiconductor device according to claim 1, further comprising a front semiconductor region having a first conductivity type and selectively provided in the surface of said SOI layer and extending from the side of said semiconductor region within the electrode region on said second electrode region side, to said gate electrode lower part, wherein

the impurity concentration of said front semiconductor region is set to be higher than that of said SOI layer and lower than that of said semiconductor region within the electrode region.

10. A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, a buried oxide film formed on said semiconductor substrate, and an SOI layer having a first conductivity type, and

at least one MOS transistor provided on said SOI layer, wherein

said at least one MOS transistor comprises;

a first electrode region and a second electrode region having a second conductivity type and selectively provided in the surface of said SOI layer,

a body region having a first conductivity type and corresponding to said SOI layer sandwiched between said first electrode region and said second electrode region,

a gate electrode provided on said body region, and

a plurality of semiconductor regions within the electrode region having a first conductivity type and provided in the surface of said first electrode region in the vicinity of said gate electrode so as to be spaced and aligned along the gate electrode and electrically connected to said body region, wherein

the peripheral region of an active region comprising said first electrode region, said second electrode region, and said body region is surrounded by a full isolation insulation film penetrating said SOI layer and reaching said buried oxide film, and

said plurality of semiconductor regions within the electrode region are arranged such that a first distance between the end of the arrangement and the nearest edge of said active region becomes the half of a second distance between said semiconductor regions within the electrode region.

11. The semiconductor device according to claim 10, wherein said first distance is set to be the half of said second distance.

12. The semiconductor device according to claim 10, wherein

said at least one MOS transistor comprises a plurality of MOS transistors in which respective gate electrodes are arranged in parallel in a gate length direction, and

said plurality of MOS transistors are provided so as to share said first electrode region between the adjacent MOS transistors.

13. The semiconductor device according to claim 12, wherein

said semiconductor region within the electrode region provided in said first electrode region shared by said adjacent MOS transistors are provided so as to continuously extend between said gate electrodes.

14. The semiconductor device according to claim 10, wherein

said at least one MOS transistor comprises an N channel MOS transistor in which said first conductivity type is a P type and said second conductivity type is an N type, and a P channel MOS transistor in which said first conductivity type is an N type and said second conductivity type is a P type,

said at least one semiconductor region within the electrode region in said N channel MOS transistor and said P channel MOS transistor comprises a plurality of semiconductor regions within the electrode region arranged so as to be space and aligned along said gate electrode, and

the distance between said semiconductor regions within the electrode region in said N channel MOS transistor is set so as to be smaller than the distance between said semiconductor regions within the electrode region in said P channel MOS transistor.

15. The semiconductor device according to claim 10, further comprising a front semiconductor region having a first conductivity type and selectively provided in the surface of said SOI layer and extending from the side of said semiconductor region within the electrode region on said second electrode region side, to said gate electrode lower part, wherein

the impurity concentration of said front semiconductor region is set to be higher than that of said SOI layer and lower than that of said semiconductor region within the electrode region.