Level shifter for semiconductor memory device implemented with low-voltage transistors

• US 20070241804A1
• Filed: 03/19/2007
• Published: 10/18/2007
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Micheloni, Rino, Campardo, Giovanni
• Granted Patent: US 7,592,849 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter is proposed. The level shifter includes a stage having a first branch and a second branch, each branch including: a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first voltage and at a second voltage higher than the first voltage in absolute value, a service terminal for receiving a third voltage higher than the second voltage in absolute value, an input circuit for coupling an intermediate node to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise, an interface circuit for coupling an output terminal to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and an output circuit for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

Claims

1. A level shifter including a stage having a first branch and a second branch, each branch including:

a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first voltage and at a second voltage higher than the first voltage in absolute value,

a service terminal for receiving a third voltage higher than the second voltage in absolute value,

an input circuit for coupling an intermediate node to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise,

an interface circuit for coupling an output terminal to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and

an output circuit for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

2. The level shifter according to claim 1, wherein in each branch the input circuit includes an input transistor having a first conduction terminal coupled to the intermediate node of the branch, a second conduction terminal coupled to the selection terminal of the branch, and a control terminal coupled to the selection terminal of the other branch.

3. The level shifter according to claim 1, wherein in each branch the interface circuit includes an interface transistor having a first conduction terminal coupled to the intermediate node, a second conduction terminal coupled to the output terminal, and a control terminal for receiving a biasing voltage comprised between the second voltage and the third voltage.

4. The level shifter according to claim 3, wherein the interface transistor has a predefined threshold voltage, the biasing voltage being at least equal to the second voltage plus the threshold voltage.

5. The level shifter according to claim 1, wherein in each branch the output circuit includes an output transistor having a first conduction terminal coupled to the service terminal of the branch, a second conduction terminal coupled to the output terminal of the branch, and a control terminal coupled to the output terminal of the other branch.

6. The level shifter according to claim 1, wherein the level shifter includes at least one further stage, all the stages being cascade connected in a sequence, and wherein for each next stage different from a first stage in the sequence each selection terminal is coupled to the corresponding output terminal of a preceding stage in the sequence.

7. The level shifter according to claim 1, wherein for each stage the difference between the second voltage and the first voltage and the difference between the third voltage and the second voltage is at most equal to a power supply voltage, each transistor being a low-voltage transistor adapted to sustain at most the power supply voltage between each pair of terminals thereof.

8. The level shifter according to claim 7, wherein each transistor is a MOSFET transistor, the input transistors and the output transistors having a first type of conductivity and the interface transistors having a second type of conductivity, the second type of conductivity being opposite to the first type of conductivity.

9. A memory device including a plurality of memory cells arranged in at least one plurality of alignments, for each plurality of alignments the memory device including means for providing a selection signal for each alignment in response to an address code, and the level shifter according to claim 1 for each alignment for receiving the corresponding selection signal and for applying the output signal to the corresponding alignment.

10. A level shifting method implemented by a level shifter including a stage having a first branch and a second branch, the method including the steps of:

receiving a selection signal at a selection terminal, the selection signal received by the first branch and the second branch being alternatively at a first voltage and at a second voltage higher than the first voltage in absolute value,

receiving a third voltage at a service terminal higher than the second voltage in absolute value,

coupling an intermediate node to the selection terminal when at the second voltage or insulating the intermediate node from the selection terminal otherwise,

coupling an output terminal to the intermediate node when coupled or insulating the output terminal from the intermediate node otherwise, and

insulating the service terminal from the output terminal when coupled or coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

11. A level shifter, comprising:

a first input stage having an input node and first and second differential output nodes;

a first cascode stage having first and second differential input nodes coupled to the first and second output nodes of the input stage, having first and second differential output nodes, and having a first bias node; and

a first output stage having first and second differential nodes coupled to the first and second output nodes of the cascode stage, having a first supply node, and operable to generate a differential output signal across the first and second differential nodes.

12. The level shifter of claim 11 wherein the input stage comprises:

an inverter having an input node coupled to the input node of the input stage and having an output node;

a first transistor having a first conduction node coupled to the input node of the input stage, a second conduction node coupled to the first output node of the input stage, and a control node coupled to the output node of the inverter; and

a second transistor having a first conduction node coupled to the output node of the inverter, a second conduction node coupled to the second output node of the input stage, and a control node coupled to the input node of the input stage.

13. The level shifter of claim 11 wherein the input stage comprises:

an inverter having an input node coupled to the input node of the input stage and having an output node;

a first MOS transistor having a first conduction node coupled to the input node of the input stage, a second conduction node coupled to the first output node of the input stage, and a gate coupled to the output node of the inverter; and

a second MOS transistor having a first conduction node coupled to the output node of the inverter, a second conduction node coupled to the second output node of the input stage, and a gate coupled to the input node of the input stage.

14. The level shifter of claim 11 wherein the input stage comprises:

an inverter having an input node coupled to the input node of the input stage and having an output node;

a first PMOS transistor having a drain coupled to the input node of the input stage, a source coupled to the first output node of the input stage, and a gate coupled to the output node of the inverter; and

a second PMOS transistor having a drain coupled to the output node of the inverter, a source coupled to the second output node of the input stage, and a gate coupled to the input node of the input stage.

15. The level shifter of claim 11 wherein the cascode stage comprises:

a first transistor having a first conduction node coupled to the first input node of the cascode stage, a second conduction node coupled to the first output node of the cascode stage, and a control node coupled to the bias node; and

a second transistor having a first conduction node coupled to the second input node of the cascode stage, a second conduction node coupled to the second output node of the cascode stage, and a control node coupled to the bias node.

16. The level shifter of claim 11 wherein the cascode stage comprises:

a first MOS transistor having a first conduction node coupled to the first input node of the cascode stage, a second conduction node coupled to the first output node of the cascode stage, and a gate coupled to the bias node; and

a second MOS transistor having a first conduction node coupled to the second input node of the cascode stage, a second conduction node coupled to the second output node of the cascode stage, and a gate coupled to the bias node.

17. The level shifter of claim 11 wherein the cascode stage comprises:

a first NMOS transistor having a source coupled to the first input node of the cascode stage, a drain coupled to the first output node of the cascode stage, and a gate coupled to the bias node; and

a second NMOS transistor having a source coupled to the second input node of the cascode stage, a drain coupled to the second output node of the cascode stage, and a gate coupled to the bias node.

18. The level shifter of claim 11 wherein the output stage comprises:

a first transistor having a first conduction node coupled to the first differential node of the output stage, a second conduction node coupled to the supply node, and a control node coupled to the second differential node of the output stage; and

a second transistor having a first conduction node coupled to the second differential node of the output stage, a second conduction node coupled to the supply node, and a control node coupled to the first differential node of the output stage.

19. The level shifter of claim 11 wherein the output stage comprises:

a first MOS transistor having a first conduction node coupled to the first differential node of the output stage, a second conduction node coupled to the supply node, and a gate coupled to the second differential node of the output stage; and

a second MOS transistor having a first conduction node coupled to the second differential node of the output stage, a second conduction node coupled to the supply node, and a gate coupled to the first differential node of the output stage.

20. The level shifter of claim 11, wherein the output stage comprises:

a first PMOS transistor having a drain coupled to the first differential node of the output stage, a source coupled to the supply node, and a gate coupled to the second differential node of the output stage; and

a second PMOS transistor having a drain coupled to the second differential node of the output stage, a source coupled to the supply node, and a gate coupled to the first differential node of the output stage.

21. The level shifter of claim 11, further comprising:

a second input stage having first and second differential input nodes coupled to the first and second differential nodes of the first output stage, and having first and second differential output nodes;

a second cascode stage having first and second differential input nodes coupled to the first and second output nodes of the second input stage, having first and second differential output nodes, and having a second bias node; and

a second output stage having first and second differential nodes coupled to the first and second output nodes of the second cascode stage, having a second supply node, and operable to generate a differential output signal across the first and second differential nodes.

22. An integrated circuit, comprising:

a level shifter, including

an input stage having an input node and first and second differential output nodes,

a cascode stage having first and second differential input nodes coupled to the first and second output nodes of the input stage, having first and second differential output nodes, and having a first bias node, and

an output stage having first and second differential nodes coupled to the first and second output nodes of the cascode stage, having a first supply node, and operable to generate a differential output signal across the first and second differential nodes.

23. A system, comprising:

an integrated circuit, including

a level shifter, including

an input stage having an input node and first and second differential output nodes,

a cascode stage having first and second differential input nodes coupled to the first and second output nodes of the input stage, having first and second differential output nodes, and having a first bias node, and

an output stage having first and second differential nodes coupled to the first and second output nodes of the cascode stage, having a first supply node, and operable to generate a differential output signal across the first and second differential nodes, and

a controller coupled to the integrated circuit.

24. The system of claim 23, herein the integrated circuit comprises a memory circuit including:

a word line coupled to one of the first and second nodes of the output stage; and

a memory cell coupled to the word line.

25. The system of claim 23 wherein the integrated circuit comprises a memory circuit including:

a word line coupled to one of the first and second nodes of the output stage;

a row decoder coupled to the input node of the input stage; and

a nonvolatile memory cell coupled to the word line.

26. A method, comprising:

receiving first and second input voltages at first and second input nodes of a first input stage;

coupling the first voltage from the first input node to a first output node of the input stage;

coupling the first voltage from the first output node to a first node of a first output stage having a supply node such that a first difference voltage between the first output node and the second input node of the input stage is less than or equal to a predetermined value;

generating on a second node of the output stage a third voltage such that a second difference voltage between the first node and the supply node of the output stage is less than or equal to the predetermined value, the third voltage being greater than a third difference voltage between the first and second voltages and less than or equal to substantially twice the third difference voltage.

27. The method of claim 26 wherein the predetermined value is substantially equal to the third difference voltage.

28. The method of claim 26 wherein coupling the first voltage from the first output node of the input stage to the first node of the output stage comprises cascoding the first voltage from the first output node to the first node.

29. The method of claim 26, further comprising:

receiving the third voltage and the first voltage at first and second input nodes of a second input stage;

coupling the third voltage from the first input node to a first output node of the second input stage;

coupling the third voltage from the first output node of the second input stage to a first node of a second output stage having a supply node such that a fourth difference voltage between the first output node and the second input node of the second input stage is less than or equal to the predetermined value; and

generating on a second node of the second output stage a fourth voltage such that a fifth difference voltage between the first node and the supply node of the second output stage is less than or equal to the predetermined value, the fourth voltage being greater than the third voltage and less than or equal to substantially three times the third difference voltage.

30. The method of claim 29 wherein coupling the third voltage from the first output node of the second input stage to the first node of the second output stage comprises cascading the third voltage from the first output node to the first node.