Precision oscillator having improved temperature coefficient control

• US 20070241833A1
• Filed: 03/31/2006
• Published: 10/18/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Nervegna, Louis J.
• Granted Patent: US 7,385,453 B2
• Time in Patent Office: Days
• US Class Current: 331/176
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

Claims

1. A free running clock circuit, comprising:

a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising;

a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit; and

an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators; and

a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

2. The free running clock circuit of claim 1, wherein the first and second comparators further comprise:

a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; and

a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto.

3. The free running clock circuit of claim 2, wherein the source degeneration circuit further comprises:

a first plurality of triode transistors connected in parallel to a first side of the current mirror; and

a second plurality of triode transistors connected in parallel to a second side of the current mirror.

4. The free running clock circuit of claim 3, wherein on-resistances of the first and the second plurality of triode transistors are weighted in a binary fashion.

5. The free running clock circuit of claim 3, wherein a positive offset voltage is generated by increasing the source degeneration on a first side of the current mirror and decreasing the source degeneration on a second side of the current mirror.

6. The free running clock circuit of claim 5, wherein a negative offset voltage is generated by decreasing the source degeneration on the first side of the current mirror and increasing the source degeneration on the second side of the current mirror.

7. The free running clock circuit of claim 1, wherein said RC timing circuit sets the frequency of said free running clock circuit and said RC timing circuit is variable.

8. The free running clock circuit of claim 7, wherein said RC timing circuit comprises:

a first RC circuit and a second RC circuit;

said first RC circuit and said second RC circuit each comprising a resistor connected through a switching device having an associated switch input between a first supply terminal and one side of a first variable capacitor array, the other side of said first variable capacitor array connected to another different supply terminal wherein current is switchable through said resistor to charge said first variable capacitor array; and

wherein the first variable capacitor array includes a course trim capacitor array and a fine trim capacitor array each programmable to control the programmable temperature profile of the switching circuit.

9. The free running clock circuit of claim 8, wherein the course trim capacitor array comprises a binary coded capacitor array.

10. The free running clock circuit of claim 8, wherein the fine trim capacitor array comprises both a binary coded capacitor array and a thermometer coded capacitor array.

11. An integrated system on a chip with serial asynchronous communication capabilities, comprising:

processing circuitry for performing predefined digital processing functions on the chip;

a free running clock circuit for generating a temperature compensative clock, comprising;

a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising;

a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit; and

an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators; and

a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit;

an asynchronous on-chip communication device for digitally communicating with an off-chip asynchronous communication device, which off-chip asynchronous communication device has an independent time reference, which communication between said on-chip communication device and said off-chip asynchronous communication device is effected without clock recovery, said asynchronous on-chip communication device having a time-base derived from said temperature compensated clock; and

wherein said temperature compensated clock provides a time reference for both said processing circuitry and said asynchronous on-chip communication device.

12. The integrated system on a chip of claim 11, wherein the first and second comparators further comprise:

a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; and

a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto.

13. The integrated system on a chip of claim 12, wherein the source degeneration circuit further comprises:

a first plurality of triode transistors connected in parallel to a first side of the current mirror; and

a second plurality of triode transistors connected in parallel to a second side of the current mirror.

14. The integrated system on a chip of claim 13, wherein on-resistances of the first and the second plurality of triode transistors are weighted in a binary fashion.

15. The integrated system on a chip of claim 13, wherein a positive offset voltage is generated by increasing the source degeneration on a first side of the current mirror and decreasing the source degeneration on a second side of the current mirror.

16. The integrated system on a chip of claim 15, wherein a negative offset voltage is generated by decreasing the source degeneration on the first side of the current mirror and increasing the source degeneration on the second side of the current mirror.

17. The integrated system on a chip of claim 11, wherein said RC timing circuit sets the frequency of said free running clock circuit and said RC timing circuit is variable.

18. The integrated system on a chip of claim 17, wherein said RC timing circuit comprises:

a first RC circuit and a second RC circuit;

said first RC circuit and said second RC circuit each comprising a resistor connected through a switching device having an associated switch input between a first supply terminal and one side of a first variable capacitor array, the other side of said first variable capacitor array connected to another different supply terminal wherein current is switchable through said resistor to charge said first variable capacitor array;

wherein the first variable capacitor array includes a course trim capacitor array and a fine trim capacitor array each programmable to control the programmable temperature profile of the switching circuit.

19. The integrated system on a chip of claim 18, wherein the course trim capacitor array comprises a binary coded capacitor array.

20. The integrated system on a chip of claim 18, wherein the fine trim capacitor array comprises both a binary coded capacitor array and a thermometer coded capacitor array.

21. A free running clock circuit, comprising:

a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising;

a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage; and

an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators, wherein said RC timing circuit comprises;

a first RC circuit and a second RC circuit;

said first RC circuit and said second RC circuit each comprising a resistor connected through a switching device having an associated switch input between a first supply terminal and one side of a first variable capacitor array, the other side of said first variable capacitor array connected to another different supply terminal wherein current is switchable through said resistor to charge said first variable capacitor array;

wherein the first variable capacitor array includes a course trim capacitor array and a fine trim capacitor array each programmable to control the programmable temperature profile of the switching circuit;

a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

22. The free running clock circuit of claim 21, wherein the course trim capacitor array comprises a binary coded capacitor array.

23. The free running clock circuit of claim 21, wherein the fine trim capacitor array comprises both a binary coded capacitor array and a thermometer coded capacitor array.

24. The free running clock circuit of claim 21, wherein the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit.

25. The free running clock circuit of claim 24, wherein the first and second comparators further comprise:

a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; and

a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto.