NAND MEMORY ARRAY INCORPORATING CAPACITANCE BOOSTING OF CHANNEL REGIONS IN UNSELECTED MEMORY CELLS AND METHOD FOR OPERATION OF SAME

• US 20070242511A1
• Filed: 06/18/2007
• Published: 10/18/2007
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Alper Ilkbahar, Andrew Walker, En-Hsing Chen, Luca Fasoli, Roy Scheuerlein, Sucheta Nallamothu
• Inventors: Fasoli, Luca, Nallamothu, Sucheta, Walker, Andrew, Chen, En-Hsing, Scheuerlein, Roy, Ilkbahar, Alper
• Granted Patent: US 7,433,233 B2
• Time in Patent Office: Days
• US Class Current: 365/185.20
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Claims

1. A method of operating an integrated circuit having a three-dimensional memory array including at least two planes of memory cells, said memory cells comprising thin film switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell.

2. The method of claim 1 wherein the biasing step further comprises decoupling the half-selected memory cell from a bias source after establishing its channel region to the first voltage.

3. The method of claim 1 wherein the biasing step further comprises decoupling the half-selected memory cell from adjacent device channel regions after establishing the half-selected memory cell channel region to the first voltage.

4. The method as recited in claim 1 wherein the biasing step comprises:

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage.

5. The method of claim 4 wherein step (d) comprises turning off at least one memory cell adjacent to the half-selected memory cell.

6. The method of claim 4 wherein step (c) comprises driving the word lines associated with the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the NAND string to a first passing voltage sufficient to turn on both programmed and unprogrammed memory cells to bias the half-selected memory cell channel to the first voltage.

7. The method of claim 6 wherein the first voltage is substantially equal to the bit line inhibit voltage.

8. The method of claim 6 wherein the first voltage is substantially less than the bit line inhibit voltage.

9. The method of claim 6 wherein step (c) further comprises driving all word lines associated with memory cells of the unselected NAND string to the first passing voltage.

10. The method of claim 4 wherein step (d) comprises driving the unselected word lines associated with the unselected NAND string to a second passing voltage different than the first passing voltage, said second passing voltage chosen such that both programmed and unprogrammed memory cells in the unselected NAND string are turned off, and such that voltage stress across unselected memory cells in a selected NAND string is reduced.

11. The method of claim 10 wherein word lines driven to the second passing voltage are driven directly from the first passing voltage to the second passing voltage.

12. The method of claim 10 wherein word lines driven to the second passing voltage are driven first from the first passing voltage to ground, and then driven to the second passing voltage.

13. The method of claim 4 further comprising:

(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;

14. A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the biasing step comprises;

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage; and

wherein step (d) comprises turning off at least one device within the first group of at least one series selection device of the unselected NAND string.