NAND-structured nonvolatile memory cell
First Claim
Patent Images
1. A non-volatile memory structure comprising a plurality of NAND flash memory cells and comprising:
- a highly doped source region coupled to a first one of the plurality of NAND flash memory cells;
a highly doped drain region coupled to a last one of the plurality of NAND flash memory cells;
a plurality of lightly doped source/drain regions shared by the plurality of NAND flash memory cells;
wherein each NAND memory cell comprises a first gate layer and a second gate layer both adapted to receive a voltage;
wherein said second gate layer of the plurality of NAND flash memory cells are connected to one another.
1 Assignment
0 Petitions
Accused Products
Abstract
A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.
-
Citations
4 Claims
-
1. A non-volatile memory structure comprising a plurality of NAND flash memory cells and comprising:
-
a highly doped source region coupled to a first one of the plurality of NAND flash memory cells;
a highly doped drain region coupled to a last one of the plurality of NAND flash memory cells;
a plurality of lightly doped source/drain regions shared by the plurality of NAND flash memory cells;
wherein each NAND memory cell comprises a first gate layer and a second gate layer both adapted to receive a voltage;
wherein said second gate layer of the plurality of NAND flash memory cells are connected to one another. - View Dependent Claims (2, 3, 4)
-
Specification