NAND-structured nonvolatile memory cell

• US 20070242514A1
• Filed: 03/10/2006
• Published: 10/18/2007
• Est. Priority Date: 03/10/2005
• Status: Abandoned Application

• Current Assignee: O2ic, Inc.
• Original Assignee: O2ic, Inc.
• Inventors: Choi, David, Choi, Kyu
• Application Number:
  US11/373,818
• Publication Number:
  US 20070242514A1
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.

Claims

1. A non-volatile memory structure comprising a plurality of NAND flash memory cells and comprising:

a highly doped source region coupled to a first one of the plurality of NAND flash memory cells;

a highly doped drain region coupled to a last one of the plurality of NAND flash memory cells;

a plurality of lightly doped source/drain regions shared by the plurality of NAND flash memory cells;

wherein each NAND memory cell comprises a first gate layer and a second gate layer both adapted to receive a voltage;

wherein said second gate layer of the plurality of NAND flash memory cells are connected to one another.

2. The non-volatile memory structure of claim 1 wherein the second gate layer of the last one of the plurality of NAND memory cells partially overlaps the first gate layer disposed therein.

3. The non-volatile memory structure of claim 2 wherein each NAND memory cell further comprises a floating poly gate layer positioned below the first gate layer and above the channel region of its associated NAND cell.

4. The non-volatile memory structure of claim 3 wherein said lightly doped source/drain regions are P⁻

regions.