METHOD AND STRUCTURE FOR SELF ALIGNED FORMATION OF A GATE POLYSILICON LAYER

• US 20070243685A1
• Filed: 01/12/2007
• Published: 10/18/2007
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Jiang, Li, Shao, Ying, Peng, Libbert, Wu, Auter
• Granted Patent: US 7,807,532 B2
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.

Claims

1. A method of fabricating an integrated circuit device, the method comprising:

providing a semiconductor substrate, the substrate comprising a surface region;

forming a pad oxide layer overlying the surface region, the pad oxide layer having a pad oxide surface region;

forming a silicon nitride layer overlying the pad oxide layer;

forming a trench region extending through an entirety of a portion of the silicon nitride layer and extending into a depth of the semiconductor substrate;

filling the trench region with an oxide material using a plasma deposition process, the oxide material extending from a bottom portion of the trench region to a vicinity of an upper surface region of the silicon nitride layer;

selectively removing the silicon nitride layer to cause formation of an isolation structure, the isolation structure extending from the bottom portion of the trench region to a height above the pad oxide surface region;

stripping the pad oxide layer;

forming a tunnel oxide overlying the surface of the semiconductor substrate;

depositing a conformal layer of polysilicon material overlying the isolation structure including the tunnel oxide structure; and

planarizing the polysilicon layer to expose a top portion of the isolation structure and form a first electrode structure and a second electrode structure separated by a portion of the isolation structure.

2. The method of claim 1 wherein the height is at least 100 Angstroms.

3. The method of claim 1 wherein the height is at least 1000 Angstroms.

4. The method of claim 1 further comprising forming a cap layer overlying a surface of the polysilicon material.

5. The method of claim 4 wherein the cap layer is CVD oxide.

6. The method of claim 1 further comprising reducing a thickness of the isolation structure using a selective etch process to form a resulting isolation structure having a final height near a vicinity above a first lower edge region of the first electrode structure and above a second lower edge region of the second electrode structure.

7. The method of claim 6 wherein the selective etch process uses a hydrofluoric acid dip species.

8. The method of claim 1 wherein the planarizing comprising:

performing a low selectivity chemical mechanical polishing process to remove a thickness of the polysilicon material;

performing a high selectivity chemical mechanical polishing process to expose a portion of the isolation material; and

performing an over polishing process once a portion of the isolation material has been exposed.

9. The method of claim 8 wherein the low selectivity chemical mechanical polishing process uses a hard pad, medium table speed, and low head rotating speed.

10. The method of claim 9 wherein the medium table speed is less than 70 revolutions per minute.

11. The method of claim 10 wherein the head rotating speed is less than 70 revolutions per minutes.

12. The method of claim 8 wherein the low selectivity chemical mechanical polishing process and the over polishing process use a down force of less than 2 pounds per square inch.

13. The method of claim 8 wherein the low selectivity chemical mechanical polishing process and the over polishing process use a table speed of less than 35 revolutions per minute and a head rotating speed of less than 35 revolutions per minute.

14. The method of claim 1 wherein the filling comprises a high density plasma process.

15. The method of claim 1 wherein the isolation structure has a width of about 0.17 microns and less.

16. The method of claim 1 wherein the first electrode structure is a first floating gate for a Flash memory device and the second electrode structure is a second floating gate for a Flash memory device.

17. The method of claim 1 wherein the planarizing also forms a dummy structure around a periphery of the first electrode structure and the second electrode structure.

18. The method of claim 17 wherein the dummy structure reduces erosion of an isolation structure spatially disposed around a vicinity of the dummy structure.