High-frequency switching device with reduced harmonics

• US 20070243849A1
• Filed: 07/24/2006
• Published: 10/18/2007
• Est. Priority Date: 04/17/2006
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Nabokin, Sergey, Prikhodko, Dima, Sprinkle, Steven C., Chiesa, Jason, Shirokov, Mikhail, Tkachenko, Gene A.
• Granted Patent: US 7,492,209 B2
• Time in Patent Office: Days
• US Class Current: 455/333
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

Claims

1. A low harmonic switching device comprising:

a first switching block comprising a first multi-gate FET, said first switching block being coupled to a first input and a shared output of said low harmonic switching device;

wherein a first capacitor is coupled between a first gate and a source of said first multi-gate FET and a second capacitor is coupled between a second gate and a drain of said first multi-gate FET so as to cause a reduction in a harmonic amplitude in said shared output.

2. The low harmonic switching device of claim 1 wherein said first multi-gate FET further comprises a third gate situated between said first gate and said second gate.

3. The low harmonic switching device of claim 1 wherein a control voltage input is coupled to said first gate and said second gate of said first multi-gate FET.

4. The low harmonic switching device of claim 1 wherein the first switching block further comprises a second multi-gate FET, wherein a source of said second multi-gate FET is coupled to said drain of said first multi-gate FET and a drain of said second multi-gate FET is coupled to said shared output.

5. The low harmonic switching device of claim 4 wherein a third capacitor is coupled between a first gate and said drain of said second multi-gate FET and a fourth capacitor is coupled between a second gate and said source of said second multi-gate FET.

6. The low harmonic switching device of claim 5 wherein a control voltage is coupled to said first gate and said second gate of said first multi-gate FET and said first gate and said second gate of said second multi-gate FET.

7. The low harmonic switching device of claim 1 wherein a resistor couples said source of said first multi-gate FET to said drain of said first multi-gate FET.

8. The low harmonic switching device of claim 3 wherein a first resistor couples said first gate of said first multi-gate FET to said control voltage and a second resistor couples said second gate of said first multi-gate FET to said control voltage.

9. The low harmonic switching device of claim 1 further comprising a second switching block, wherein said second switching block is coupled to a second input and said shared output of said low harmonic switching device.

10. The low harmonic switching device of claim 9 wherein said first input is coupled to said shared output when a first control voltage turns said first switching block on and a second control voltage turns said second switching block off and said second input is coupled to said shared output when said second control voltage turns said second switching block on and said first control voltage turns said first switching block off.

11. A low harmonic switching device comprising:

a first switching block comprising a first multi-gate FET, said first switching block being coupled to a first input and a shared output of said low harmonic switching device;

wherein a reference voltage is coupled to a source and a drain of said first multi-gate FET to cause a reduction in harmonic amplitude in said shared output.

12. The low harmonic switching device of claim 11 wherein a first capacitor is coupled between a first gate and said source of said first multi-gate FET and a second capacitor is coupled between a second gate and said drain of said first multi-gate FET.

13. The low harmonic switching device of claim 12 wherein said first multi-gate FET further comprises a third gate situated between said first gate and said second gate.

14. The low harmonic switching device of claim 12 further comprising a control voltage input, wherein said control voltage input is coupled to said first gate and said second gate of said first multi-gate FET.

15. The low harmonic switching device of claim 14 wherein said control voltage input is configured to provide a low voltage to turn said off said first multi-gate FET and a high voltage to turn on said first multi-gate FET, wherein said reference voltage comprises said high voltage.

16. The low harmonic switching device of claim 12 wherein said first switching block further comprises a second multi-gate FET, wherein a source of said second multi-gate FET is coupled to a drain of said first multi-gate FET and a drain of said second multi-gate FET is coupled to said shared output.

17. The low harmonic switching device of claim 16 wherein a third capacitor is coupled between a first gate and said drain of said second multi-gate FET and a fourth capacitor is coupled between a second gate and said source of said second multi-gate FET.

18. The low harmonic switching device of claim 11 wherein said reference voltage is coupled to said source of said first of multi-gate FET by a first resistor and said reference voltage is coupled to said drain of first multi-gate FET by a second resistor.

19. The low harmonic switching device of claim 11 further comprising a second switching block, wherein said second switching block is coupled to a second input and said shared output of said low harmonic switching device.

20. The low harmonic switching device of claim 19 wherein said first input is coupled to said shared output when a first control voltage turns said first switching block on and a second control voltage turns said second switching block off and said second input is coupled to said shared output when said second control voltage turns said second switching block on and said first control voltage turns said first switching block off.