Configurable IC's with dual carry chains

• US 20070244959A1
• Filed: 03/15/2005
• Published: 10/18/2007
• Est. Priority Date: 03/15/2005
• Status: Abandoned Application

• Current Assignee: Tabula Incorporated
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Redgrave, Jason
• Application Number:
  US11/082,220
• Publication Number:
  US 20070244959A1
• Time in Patent Office: Days
• US Class Current: 708/700
• CPC Class Codes: G06F 2207/3868 Bypass control, i.e. possibility to transfer an operand unchanged to the output
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages

Abstract

Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each of several sets of associated configurable logic circuits, the configurable IC includes first and second circuitry for establishing carry signal flow in two directions through the configurable logic circuits. A carry signal flow representing a flow of a carry signal during an add operation performed by a set of associated configurable logic circuits. In some embodiments, the two carry signals flow in opposing directions through the set of logic circuits.

Claims

1. A configurable IC comprising:

a) a plurality of configurable logic circuits, wherein the logic circuits include a plurality of sets of associated configurable logic circuits; and

b) for each of a plurality of sets of associated configurable logic circuits, first and second circuitry for establishing carry signal flow in two directions through the configurable logic circuits, a carry signal flow representing a flow of a carry signal during an add operation performed by a set of associated configurable logic circuits.

2. The configurable IC of claim 1, wherein the two directions are two opposing directions.

3. The configurable IC of claim 2,

wherein during an add operation, a particular set of logic circuits receives two sets of signals to add,

wherein each particular logic circuit in the particular set of logic circuits receives one signal from each of the two received sets,

wherein in one flow of the carry signal, a particular signal received by at least one particular logic circuit is defined to be a first particular bit in the particular signal'"'"'s signal set, while in the other flow of the carry signal, the particular signal is defined to be a second particular bit in the particular signal set.

4. The configurable IC of claim 1, wherein each set of logic circuits performs a set of carry operations.

5. The configurable IC of claim 4, wherein each carry operation is a one-bit carry operation associated with a one-bit add operation.

6. The configurable IC of claim 1, wherein each set of configurable logic circuits are also for performing operations unrelated to add or subtract operations.

7. The configurable IC of claim 6, wherein to perform any operation, each configurable logic circuit receives a configuration data set that configures the logic circuit to perform the operation.

8. The configurable IC of claim 1 further comprising a plurality of carry circuits for performing a plurality of carry operations.

9. The configurable IC of claim 8, wherein each set of configurable logic circuits includes a set of carry circuits.

10. The configurable IC of claim 9, wherein the set of carry circuits for set of logic circuits includes one shared circuit that performs a carry chain operation for all logic circuits in the set.

11. The configurable IC of claim 10, wherein each set of configurable logic circuits are placed around the shared carry circuit.

12. The configurable IC of claim 8, wherein each carry circuit receives propagate and generate signals from a configurable logic circuit, and based on the propagate and generate signals generates a carry signal.

13. The configurable IC of claim 9, wherein each set of carry circuits includes a carry chain formed by serially connecting a set of one-bit carry circuits.

14. The configurable IC of claim 13, wherein the carry chain is a Manchester carry chain.

15. A electronic device comprising:

a configurable integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits, wherein the logic circuits include a plurality of sets of associated configurable logic circuits; and

for each of a plurality of sets of associated configurable logic circuits, first and second circuitry for establishing carry signal flow in two opposing directions through the configurable logic circuits, a carry signal flow representing a flow of a carry signal during an add operation performed by a set of associated configurable logic circuits.

16. The electronic device of claim 15,

wherein during an add operation, a particular set of logic circuits receives two sets of signals to add,

wherein each particular logic circuit in the particular set of logic circuits receives one signal from each of the two received sets,

wherein in one flow of the carry signal, a particular signal received by at least one particular logic circuit is defined to be a first particular bit in the particular signal'"'"'s signal set, while in the other flow of the carry signal, the particular signal is defined to be a second particular bit in the particular signal set.

17. The electronic device of claim 15, wherein each set of logic circuits performs a set of carry operations.

18. The electronic device of claim 17, wherein each carry operation is a one-bit carry operation associated with a one-bit add operation.

19. The electronic device of claim 15, wherein each set of configurable logic circuits are also for performing operations unrelated to add or subtract operations.

20. The electronic device of claim 19, wherein to perform any operation, each configurable logic circuit receives a configuration data set that configures the logic circuit to perform the operation.

21. The electronic device of claim 15, wherein each set of configurable logic circuits includes a set of carry circuits for performing a plurality of carry operations.

22. The electronic device of claim 21, wherein the set of carry circuits for set of logic circuits includes one shared circuit that performs a carry chain operation for all logic circuits in the set.