System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol

• US 20070245044A1
• Filed: 07/06/2006
• Published: 10/18/2007
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Boucard, Philippe, Douady, Cesar
• Granted Patent: US 8,645,557 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol The system of interconnections (20) for external functional blocks on a chip provided with a single configurable communication protocol, comprises two physically separate communication networks (21, 22): a request network (21) for transmitting request messages from an initiating block (23, 24, 25, 26) to a recipient block (27, 28, 29, 30, 31) and a response network (22) for transmitting response messages from a recipient block (27, 28, 29, 30, 31) to an initiating block (23, 25, 26). The response messages include additional information making said request (21) and response (22) networks able to respectively manage the request messages and the response messages independently.

Claims

1. System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol, the system comprising two physically separate communication networks, a request network for transmitting request messages from an initiating block to a recipient block and a response network for transmitting response messages from a recipient block to an initiating block, wherein the response messages include additional information making said request and response networks able to respectively manage the request messages and the response messages independently.

2. System according to claim 1, wherein said protocol is organized in a plurality of independent layers, said independent layers comprising a transport layer defining the structure of a data packet, and a physical layer defining the signals interchanged at the interfaces of the elements of the system of interconnections, address, data size and operation information being contained in the headers of the data packets.

3. System according to claim 1, wherein said additional information of the response message data packets includes information representative of the operation carried out, and information representative of the size of the data associated with said operation carried out.

4. System according to claim 1, wherein the operation is a data read or data write.

5. System according to claim 1, wherein, following a read of data that is incomplete or unaligned in relation to the memory space accessed in said read, the packets of the response message associated with said read include, at a predetermined position, said data that has been read.

6. System according to claim 1, wherein, following a read of data that is incomplete or unaligned in relation to the memory space accessed in said read, the headers of the packets of the response message associated with said read include information for aligning said data that has been read in relation to said memory space accessed.

7. System according to claim 1, wherein the interface between two elements of the system of interconnections comprises:

means for receiving or transferring a clock timing signal;

means for transferring or receiving signals for stopping or starting said elements independently;

means of transferring flow control signals relating to the clock cycles,

means of transferring data packet delimiting signals, and

means of transferring signals of configurable size for transmitting the content of the data packets.

8. System according to claim 7, in which the interface between two elements of the system of interconnections also comprises signal generation means for favoring the transmission of some messages over others.

9. System according to claim 1, wherein the headers of the data packets include an available space reserved for the use of the initiating blocks.

10. System according to claim 1, wherein the data packets are of variable length, equal to a multiple of an elementary quantity of data, a system link being programmable by the ratio between the quantity of data that it can transmit in each clock cycle and said elementary quantity of data.

11. System according to claim 1, wherein the links include means of changing the clock frequency, and/or means of deleting data holes in the data packets in case of predictable hole ratios, and/or means of changing the serialization of the packets.

12. System according to claim 1, wherein the elements of the system of interconnections are configurable by software means via a separate network.

13. System according to claim 12, in which said separate network is able to operate at a low bit rate compared to the average bit rate in the system of interconnections.

14. Generators of configurable IP blocks for constructing a system in modular fashion according to claim 1, using standard interfaces.

15. Generators according to claim 14, comprising:

a generator of configurable protocol IP blocks;

generators of network interface IP blocks between said configurable protocol and other communication protocols, generators of switch IP blocks,

generators of IP blocks for changing clock domain, compacting data packets, transporting packets over long distances, and programming ratios between the quantity of data that a link can transmit in each clock cycle and said elementary quantity of data, and

generators of IP blocks of a separate network for configuring the elements of the system of interconnections.