Multiplexing a parallel bus interface and a flash memory interface

• US 20070245061A1
• Filed: 04/13/2006
• Published: 10/18/2007
• Est. Priority Date: 04/13/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Harriman, David
• Application Number:
  US11/404,170
• Publication Number:
  US 20070245061A1
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for multiplexing a parallel bus interface with a flash memory interface. In some embodiments, an integrated circuit includes a parallel bus interface to communicate parallel bus interface signals. The integrated circuit may also include logic to multiplex flash memory device interface signals and parallel bus interface signals on the parallel bus interface.

Claims

1. An integrated circuit comprising:

a parallel bus interface to communicate parallel bus interface signals; and

logic coupled with the parallel bus interface, the logic to multiplex non-volatile storage device interface signals with the parallel bus interface signals on the parallel bus interface.

2. The integrated circuit of claim 1, wherein the logic coupled with the parallel bus interface comprises:

logic to multiplex flash memory interface signals with the parallel bus interface signals on the parallel bus interface.

3. The integrated circuit of claim 2, wherein the logic to multiplex flash memory interface signals with the parallel bus interface signals on the parallel bus interface comprises:

logic to multiplex NAND flash interface signals with the parallel bus interface signals on the parallel bus interface.

4. The integrated circuit of claim 3, wherein the parallel interface is a peripheral component interconnect (PCI) interface to communicate PCI interface signals.

5. The integrated circuit of claim 4, wherein the logic to multiplex NAND flash interface signals with the PCI interface signals on the PCI interface comprises:

logic to dynamically multiplex NAND flash interface signals with the PCI interface signals on the PCI interface.

6. The integrated circuit of claim 4, wherein the logic to multiplex NAND flash interface signals with the PCI interface signals on the PCI interface comprises:

logic to statically configure whether the PCI interface communicates NAND flash interface signals or the PCI interface signals.

7. The integrated circuit of claim 4, wherein the PCI interface is to multiplex a ready/busy signal (RB#) and a request signal (REQx#) on a common pin.

8. The integrated circuit of claim 4, wherein the PCI interface is to multiplex a chip select signal (CS#) and a grant signal (GNTx#) on a common pin.

9. The integrated circuit of claim 1, wherein the integrated circuit includes an input/output controller.

10. A method comprising:

selecting whether to communicate with a parallel bus device or a flash memory device via a parallel bus interface; and

communicating with the flash memory device via the parallel bus interface, if the flash memory device is selected.

11. The method of claim 10, wherein the parallel bus device includes a peripheral component interconnect (PCI) device, the flash memory device includes a NAND flash device, and the parallel bus interface is a PCI interface.

12. The method of claim 11, wherein selecting whether to communicate with the parallel bus device or the flash memory device via the parallel bus interface comprises:

dynamically selecting whether to communicate with the parallel bus device or the flash memory device via the parallel bus interface.

13. The method of claim 11, wherein selecting whether to communicate with the parallel bus device or the flash memory device via the parallel bus interface comprises:

statically selecting whether to communicate with the parallel bus device or the flash memory device via the parallel bus interface.

14. The method of claim 11, wherein communicating with the NAND flash memory device via the PCI interface, if the NAND flash memory device is selected comprises:

multiplexing a ready/busy signal (RB#) on a request signal (REQx#) pin of the PCI interface; and

multiplexing a chip select signal (CS#) on a grant signal (GNTx#) pin of the PCI interface.

15. A system comprising;

a parallel bus having a plurality of input/output lines;

an integrated circuit coupled with the parallel bus, the integrated circuit including

a parallel bus interface to communicate parallel bus interface signals; and

logic coupled with the parallel bus interface, the logic to multiplex flash memory device interface signals with the parallel bus interface signals on the parallel bus interface; and

a flash memory device coupled with at least some of the plurality of input/output lines to provide a first memory channel.

16. The system of claim 15, wherein the parallel bus includes a peripheral component interconnect (PCI) bus and the parallel bus interface includes a PCI interface.

17. The system of claim 16, further comprising:

a second flash memory device coupled with at least some of the plurality of input/output lines to provide a second memory channel.

18. The system of claim 17, further comprising:

a third flash memory device coupled with the second flash memory device to increase a capacity of the second memory channel.

19. The system of claim 18, wherein the second flash memory device and the third flash memory device are collocated within a single package.

20. The system of claim 15, wherein the integrated circuit includes an input/output controller.