Cycle count storage methods

• US 20070245068A1
• Filed: 04/13/2006
• Published: 10/18/2007
• Est. Priority Date: 04/13/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Yero, Emilio
• Granted Patent: US 7,451,264 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.

Claims

1. A method of managing erase blocks of a NAND flash memory array formed on a first substrate, the array under the control of a controller on a second substrate, the NAND flash memory array having a minimum unit of erase of a block, a block including two or more pages, comprising:

reading a hot count value from a block, the hot count value representing the number of times the block has been erased;

storing the hot count value in a register that is located on the first substrate;

comparing the hot count value with a predetermined value;

if the hot count value does not exceed the predetermined value then erasing all the data in the block, incrementing the hot count value and writing the incremented hot count value to the block; and

if the hot count value exceeds the predetermined value then recording that the block is not for subsequent storage of data.

2. The method of claim 1 wherein the hot count value is stored in memory cells storing one bit per memory cell and host data stored in the block are stored in memory cells storing two or more bits per memory cell.

3. The method of claim 1 wherein the register is initialized to a non-zero number.

4. The method of claim 1 wherein the block is one of a plurality of blocks that form a plane and the register is dedicated to the plane, additional registers being used for additional planes.

5. The method of claim 1 wherein the plane, the additional planes, the register and the additional registers are on the first substrate.

6. The method of claim 1 wherein an indication is sent to the controller if the hot count exceeds the predetermined value.

7. The method of claim 1 wherein the hot count value is read from an overhead data area of the block and the incremented hot count value is written to the overhead data area of the block.

8. A method of using a hot count in a flash memory system including a NAND flash memory array on a first substrate and a memory controller on a second substrate, the NAND flash memory array having a minimum unit of erase of a block, the hot count representing the number of times the block has been erased, a block containing two or more pages, where a page is a minimum unit of programming, comprising:

reading the hot count from the block;

comparing the hot count with a predetermined value in a comparing circuit on the first substrate; and

if the hot count exceeds the predetermined value then changing an operating condition of the block.

9. The method of claim 8 wherein changing the operating condition results in the block being disabled.

10. The method of claim 8 wherein changing the operating condition results in a change in at least one voltage used in accessing the block.

11. The method of claim 10 wherein the at least one voltage includes at least one of a programming voltage and an erase voltage.

12. The method of claim 8 further comprising comparing the hot count with additional predetermined values and selecting a set of operating conditions based on the comparison with the predetermined value and additional predetermined values.

13. The method of claim 8 wherein the hot count is stored in an overhead data area of the block in a binary format and host data are stored in a host data area of the block in a multi-level format.

14. A method of operating a flash memory array having a minimum unit of erase of a block, the memory array having a plurality of planes including at least a first plane and a second plane, each of the plurality of planes having its own row and column decoder circuits, comprising:

maintaining a first hot count for a first block in the first plane by copying a first hot count value from the first block to a first register, incrementing the first hot count value, erasing the first block and writing the incremented first hot count value to the first block;

comparing the first hot count value to a threshold value and operating the first block in a first mode if the first hot count value is less than the threshold value and operating the first block in a second mode if the first hot count value is greater than the threshold value;

maintaining a second hot count for a second block in the second plane by copying a second hot count value from the second block to a second register, incrementing the second hot count value, erasing the second block and writing the incremented second hot count value to the second block; and

comparing the second hot count value to the threshold value and operating the second block in a first mode if the second hot count value is less than the threshold value and operating the second block in a second mode if the second hot count value is greater than the threshold value.

15. The method of claim 14 wherein the plurality of planes are controlled by a single controller.

16. The method of claim 15 wherein the plurality of planes is on one or more memory chips and the controller is on a separate controller chip.

17. The method of claim 16 wherein the comparing the first hot count value to a threshold value and the comparing the second hot count to the threshold value are performed by circuits on the one or more memory chips.

18. The method of claim 17 wherein, in the second mode the first block is disabled and an indication that the first block is disabled is sent to the controller.

19. The method of claim 14 wherein, in the first mode the first block uses a first set of operating voltages and in the second mode the first block uses a second set of operating voltages.

20. The method of claim 14 wherein the flash memory array is a NAND array.

21. The method of claim 14 wherein a block of the flash memory array comprises two or more pages and each of the two or more pages contains two or more sectors of data.