Memory compression method and apparatus for heterogeneous processor architectures in an information handling system

• US 20070245097A1
• Filed: 03/23/2006
• Published: 10/18/2007
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: LinkedIn Corporation (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Gschwind, Michael, Minor, Barry
• Granted Patent: US 7,849,241 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/253 Centralized memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions

Abstract

The disclosed heterogeneous processor compresses information to more efficiently store the information in a system memory coupled to the processor. The heterogeneous processor includes a general purpose processor core coupled to one or more processor cores that exhibit an architecture different from the architecture of the general purpose processor core. In one embodiment, the processor dedicates a processor core other than the general purpose processor core to memory compression and decompression tasks. In another embodiment, system memory stores both compressed information and uncompressed information.

Claims

1. A method of compressing and decompressing information in a heterogeneous multi-core processor, the method comprising:

processing information by a first processor core exhibiting a first architecture;

processing information by a second processor core exhibiting a second architecture;

compressing, by the second processor core, information to be sent by the heterogeneous multi-core processor to a system memory for storage therein as compressed information; and

decompressing, by the second processor core, compressed information received from the system memory for use as uncompressed information by the heterogeneous processor.

2. The method of claim 1, wherein the first architecture is a general purpose processor core and the second architecture is a special purpose processor core that performs tasks assigned by the first processor core.

3. The method of claim 1, further comprising storing, by the heterogeneous multi-core processor, both compressed information and uncompressed information in the system memory which acts as a shared memory.

4. The method of claim 1, wherein a memory flow controller in the second processor core communicates compressed information and uncompressed information to and from the system memory.

5. The method of claim 1, wherein the second processor core is dedicated to compressing and decompressing information.

6. The method of claim 1, wherein the first processor core and the second processor core share compressing and decompressing information tasks.

7. The method of claim 1, wherein the second processor core speculatively decompresses information in the system memory that may be needed by the first processor core, and the second processor core speculatively compresses information for storage in the system memory.

8. The method of claim 1, further comprising changing, by the processor, a ratio of compressed information to uncompressed information in the system memory.

9. The method of claim 1, wherein the first processor core performs other tasks while the second processor core is compressing or decompressing information.

10. A heterogeneous multi-core processor comprising:

a first processor core exhibiting a first architecture;

a second processor core exhibiting a second architecture that compresses information to provide compressed information and that decompresses compressed information to provide uncompressed information; and

a bus coupling the first processor core to the second processor core, the bus being adapted to communicate the compressed information and uncompressed information to and from a system memory.

11. The heterogeneous multi-core processor of claim 10, wherein the first architecture is a general purpose processor core and the second architecture is a special purpose processor core that performs tasks assigned by the first processor core.

12. The heterogeneous multi-core processor of claim 10, wherein the system memory comprises a shared memory that stores both compressed information and uncompressed information.

13. The heterogeneous multi-core processor of claim 10, wherein the second processor core is dedicated to compressing and decompressing information.

14. The heterogeneous multi-core processor of claim 10, wherein first processor core and the second processor core share compressing and decompressing information tasks.

15. The heterogeneous multi-core processor of claim 10, wherein the second processor core speculatively decompresses information in the system memory that may be needed by the first processor core, and the second processor core speculatively compresses information for storage in the system memory.

16. An information handling system (IHS) comprising:

a heterogeneous processor including;

a first processor core exhibiting a first architecture;

a second processor core exhibiting a second architecture that compresses information to provide compressed information and that decompresses compressed information to provide uncompressed information;

a bus coupling the first processor core to the second processor core; and

a system memory, coupled to the heterogeneous processor, that stores the compressed information and the uncompressed information.

17. The IHS of claim 16, wherein the first architecture is a general purpose processor core and the second architecture is a special purpose processor core that performs tasks assigned by the first processor core.

18. The IHS of claim 16, wherein the second processor core is dedicated to compressing and decompressing information.

19. The IHS of claim 16, wherein the first processor core and the second processor core share compressing and decompressing information tasks.

20. The IHS of claim 16, wherein the second processor core speculatively decompresses information in the system memory that may be needed by the first processor core, and the second processor core speculatively compresses information for storage in the system memory.