Method and Device for Switching Between at Least Two Operating Modes of a Processor Unit

• US 20070245133A1
• Filed: 08/20/2004
• Published: 10/18/2007
• Est. Priority Date: 10/24/2003
• Status: Abandoned Application

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Weiberle, Reinhard, Kottke, Thomas, Steininger, Andreas
• Application Number:
  US10/577,009
• Publication Number:
  US 20070245133A1
• Time in Patent Office: Days
• US Class Current: 712/229
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A method and a device are described for switching between at least two operating modes of a processor unit including at least two execution units for running programs, at least one identifier being assigned to at least the programs which differentiates between the at least two operating modes, and switching between the operating modes is performed as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.

Claims

1-18. -18. (canceled)

19. A method for switching between at least two operating modes of a processor unit that includes at least two execution units for running programs, comprising:

assigning at least one identifier to at least the programs, the identifier allowing a differentiation between the at least two operating modes;

switching between the operating modes as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.

20. The method as recited in claim 19, wherein the programs contain task programs or constitute them, and the identifier is assigned to the corresponding individual task programs.

21. The method as recited in claim 19, wherein the programs are made up of individual program segments or contain them, and the identifier is assigned to the corresponding individual program segments.

22. The method as recited in claim 19, wherein the programs are made up of individual program instructions, and the identifier is assigned to the corresponding individual program instructions.

23. The method as recited in claim 19, wherein the programs are part of an operating system of the processor unit or constitute the operating system.

24. The method as recited in claim 19, wherein the programs are used for controlling operating sequences of a vehicle.

25. The method as recited in claim 19, wherein a first operating mode is provided which corresponds to a safety mode in which the two execution units run identical programs redundantly.

26. The method as recited in claim 25, wherein conditions or results obtained while the programs are run are compared for agreement, errors being detected if there is a discrepancy.

27. The method as recited in claim 25, wherein the programs are run synchronously.

28. The method as recited in claim 19, wherein in the second operating mode, which corresponds to a performance mode, each execution unit runs different programs.

29. The method as recited in claim 19, wherein the identifier is in the form of at least one bit.

30. The method as recited in claim 19, wherein a program instruction provided that generates an identifier indicating if the program is to be run in the first or second operating mode.

31. The method as recited in claim 19, wherein the identifier is written to a specific memory area.

32. The method as recited in claim 31, wherein the identifier is generated by an instruction provided in an instruction set of the processor unit.

33. The method as recited in claim 32, wherein the identifier is generated by a write instruction.

34. A device for switching between at least two operating modes of a processor unit that includes at least two execution units for running programs, comprising:

an arrangement for assigning at least one identifier to at least the programs, the identifier allowing a differentiation between the at least two operating modes;

an arrangement for switching between the operating modes as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.

35. The device as recited in claim 34, further comprising:

at least duplicate arithmetic-logic units provided correspondingly as at least two execution units.

36. A processor unit for running programs, comprising:

at least two execution units;

a switching arrangement via which it is possible to switch between at least two operating modes of the processor unit, wherein;

the switching arrangement assigns at least one identifier to at least the programs, the at least one identifier allowing a differentiation between the two operating modes, and the switching arrangement being designed in such a way that the switching arrangement switches between the operating modes as a function of the identifier, and the processor unit runs the programs according to the assigned operating mode.