Application Specific Distributed Test Engine Architecture System And Method

• US 20070245199A1
• Filed: 03/30/2007
• Published: 10/18/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Robert Pochowski
• Original Assignee: Robert Pochowski
• Inventors: Pochowski, Robert
• Granted Patent: US 7,552,370 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even the number of test engines can be changed as different devices are tested, or as different test methodologies are used with the system. This can be done by including the test engine configuration as a part of the application files that are loaded during the system set-up. This approach differs from conventional testing systems which limit testing to a fixed, limited, or standard stimulus/response engine configuration intended to test a variety of devices. Some of the benefits of the Application Specific Distributed Test Engine Architecture include: (1) a very high test throughput, (2) the ability to adapt system functionality and capabilities to meet different and new, unforeseen device test requirements on a lot-by-lot basis on a production test floor, and (3) the ability to change the number of test engines to optimize tester channels and system utilization.

Claims

1. A distributed test system for testing one or more devices under test including a first device under test, wherein said devices under test include integrated circuits, the distributed test system comprising:

a first application specific test engine (ASTE) that generates first test signals for the first device under test, wherein the first ASTE is programmable in the testing environment to enable modification of said first test signals based upon a type of said first device under test;

an existing test unit to generate a defined set of defined test signals; and

a switch matrix including a first switch for connecting the first device under test to one of the first ASTE or the existing test unit; and

a controller, coupled to the switch matrix and the one or more ASTEs, for determining connections made by said switch matrix;

wherein said first ASTE transmits said first test signals to the first device under test and receives a first response based upon said first test signals from the first device under test when the first switch couples the first ASTE to the first device under test.

2. The distributed test system of claim 1, wherein the first ASTE identifies errors in the first response representing one or more errors in the first device under test.

3. The distributed test system of claim 1, wherein the first test signals are programmed based upon a type of the first device under test.

4. The distributed test system of claim 1, wherein said first ASTE is programmable and includes at least one of field programmable gate arrays, programmable logic devices, or complex programmable logic devices.

5. The distributed test system of claim 1, wherein the first ASTE includes a first T-state protocol generator that converts first test commands to said first test signals, wherein said first test signals are compatible with a first protocol used by the first device under test, wherein said first test commands are testing commands that are not consistent with the first protocol.

6. The distributed test system of claim 1, wherein said first ASTE comprises:

a first memory unit; and

a first processor wherein a memory of the first device under test is mapped into the first memory unit.

7. The distributed test system of claim 1, further comprising:

a second ASTE that generates first test signals for a second device under test of said one or more devices under test, wherein the second ASTE is programmable in the testing environment to enable modification of said second test signals based upon a type of said second device under test; and

a second switch of said switch matrix for connecting the second device under test to one of the second ASTE or the existing test unit;

wherein said second ASTE transmits said second test signals to the second device under test and receives a second response based upon said second test signals from the second device under test when the second switch couples the second ASTE to the second device under test.

8. The distributed test system of claim 7, wherein the second ASTE identifies errors in the second response representing one or more errors in the second device under test.

9. The distributed test system of claim 7, wherein the second test signals are programmed based upon a type of the second device under test.

10. The distributed test system of claim 7, wherein said second ASTE is programmable and includes at least one of field programmable gate arrays, programmable logic devices, or complex programmable logic devices.

11. The distributed test system of claim 7, wherein the second ASTE includes a second T-state protocol generator that converts second test commands to said second test signals, wherein said second test signals are compatible with a second protocol used by the second device under test, wherein said second test commands are testing commands that are not consistent with the second protocol.

12. The distributed test system of claim 7, wherein said second ASTE comprises:

a second memory unit; and

a second processor wherein a memory of the second device under test is mapped into the second memory unit.

13. A distributed test system for testing one or more devices under test including a first device under test, wherein said devices under test include integrated circuits, the distributed test system comprising:

a first application specific test engine (ASTE) that generates first test signals for the first device under test, wherein the first ASTE is programmable in the testing environment to enable modification of said first test signals based upon a type of said first device under test; and

wherein said first ASTE transmits said first test signals to the first device under test and receives a first response based upon said first test signals from the first device under test when the first switch couples the first ASTE to the first device under test.

14. The distributed test system of claim 13 further comprising:

a shared input unit to generate a set of shared test signals;

a switch matrix including a first switch for connecting the first device under test to one of the first ASTE or the shared input unit; and

a controller, coupled to the switch matrix, the one or more ASTEs and the shared input unit, for determining connections made by said switch matrix.

15. The distributed test system of claim 13, wherein the first ASTE identifies errors in the first response representing one or more errors in the first device under test.

16. The distributed test system of claim 13, wherein the first test signals are programmed based upon a type of the first device under test.

17. The distributed test system of claim 13, wherein said first ASTE is programmable and includes at least one of field programmable gate arrays, programmable logic devices, or complex programmable logic devices.

18. The distributed test system of claim 13, wherein the first ASTE includes a first T-state protocol generator that converts first test commands to said first test signals, wherein said first test signals are compatible with a first protocol used by the first device under test, wherein said first test commands are testing commands that are not consistent with the first protocol.

19. The distributed test system of claim 13, further comprising:

a second ASTE that generates first test signals for a second device under test of said one or more devices under test, wherein the second ASTE is programmable in the testing environment to enable modification of said second test signals; and

wherein said second ASTE transmits said second test signals to the second device under test and receives a second response based upon said second test signals from the second device under test when the second switch couples the second ASTE to the second device under test.

20. The distributed test system of claim 19, further comprising a second switch of said switch matrix for connecting the second device under test to one of the second ASTE or the shared input unit.

21. The distributed test system of claim 13, wherein said first ASTE comprises:

a first memory unit; and

a first processor wherein a memory of the first device under test is mapped into the first memory unit.

22. A method for testing one or more devices under test, including a first device under test, wherein the devices under test comprise integrated circuits, the method comprising:

loading defined test program into an existing test unit;

loading configuration files, including a programmable test program into a first testing unit in the testing environment based upon a type of the device under test;

coupling the first device under test to one of said existing test unit or said first testing unit based upon a type of testing;

generating first test signals from said first testing unit;

transmitting said first test signals to the first device under test;

receiving a first response based upon said first test signals from the first device under test when the first switch couples the first testing unit to the first device under test; and

identifying errors in said first response representing one or more errors in the first device under test.

23. The method of claim 22, further comprising the step of:

reprogramming said first test signals based upon a type of the first device under test;

loading new configurations files including said reprogrammed first test signals into the first testing unit.

24. The method of claim 22, wherein said configuration files include first test commands, further comprising the step of:

converting first test commands to said first test signals, wherein said first test signals are compatible with a first protocol used by the first device under test, wherein said first test commands are testing commands that are not consistent with the first protocol.

25. The method of claim 22 further comprising the step of:

mapping a memory in the first device under test into a first memory of said first testing unit.