Semiconductor apparatus and test method therefor
First Claim
1. A semiconductor apparatus comprising:
- a memory chip including a memory circuit to be tested; and
a logic chip including an internal logic circuit and a test processor connected with the internal logic circuit and the memory circuit to access the memory circuit through an external terminal and test the memory circuit, the test processor including a high-speed test control circuit capable of selecting a signal transfer rate between the external terminal and the memory circuit according to a test speed when testing the memory circuit.
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Accused Products
Abstract
A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and supplies a test signal input from an external terminal to the access terminal to thereby test the memory circuit. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed.
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Citations
20 Claims
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1. A semiconductor apparatus comprising:
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a memory chip including a memory circuit to be tested; and a logic chip including an internal logic circuit and a test processor connected with the internal logic circuit and the memory circuit to access the memory circuit through an external terminal and test the memory circuit, the test processor including a high-speed test control circuit capable of selecting a signal transfer rate between the external terminal and the memory circuit according to a test speed when testing the memory circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A test method of a semiconductor apparatus comprising:
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supplying a test signal from an external terminal through a high-speed test control circuit included in a test processor connected with an internal logic circuit on a logic chip and capable of selecting a signal transfer rate between the external terminal and a memory circuit to be tested on a memory chip according to a test speed; and performing test on the memory circuit. - View Dependent Claims (18, 19, 20)
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Specification