Multi-mode processor

• US 20070245221A1
• Filed: 04/02/2007
• Published: 10/18/2007
• Est. Priority Date: 11/16/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lakkis, Ismail
• Granted Patent: US 8,583,995 B2
• Time in Patent Office: Days
• US Class Current: 714/783
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/1505 Golay Codes
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding
• CPC Class Codes: H03M 13/618 Shortening and extension of codes

Abstract

An apparatus is configured to perform both Fourier transform processing and Golay code processing. Each of a plurality of processing elements comprises a delay element configured for providing a predetermined delay to at least a first input signal, at least one seed vector insertion element configured for multiplying at least a second input signal by at least one seed-vector value for producing at least one scaled input signal value, and at least one multiplexer configurable by at least one control signal for selecting an operating mode of the apparatus. At least one twiddle-factor multiplier is coupled between stages of the processing elements and employed for Fourier transform processing. The apparatus may be configured to perform both multi-mode and multi-band operation. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Claims

1. An apparatus configured to perform both Fourier transform processing and Golay code processing, the apparatus comprising:

a plurality of processing elements, each of the processing elements comprising;

at least one delay element configured for providing a predetermined delay to at least a first input signal,

at least one seed vector insertion element configured for multiplying at least a second input signal by at least one seed-vector value for producing at least one scaled input signal value, and

at least one multiplexer configurable by at least one control signal for selecting an operating mode of the apparatus; and

at least one twiddle-factor multiplier coupled to at least one output of at least one of the plurality of processing elements.

2. The apparatus recited in claim 1, wherein each of the processing elements further comprises a set of multiplexers coupled to the at least one delay element and the at least one seed vector insertion element, the set of multiplexers configured for selecting at least one of a plurality of scaled input signal values.

3. The apparatus recited in claim 1, configured for performing at least one of a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT).

4. The apparatus recited in claim 1, being configurable via at least one control signal to perform at least one of Golay processing and Fourier transform processing.

5. The apparatus recited in claim 1, being configured for Fourier transform processing and bypassing the at least one twiddle-factor multiplier to perform a fast Walsh-Hadamard transform.

6. The apparatus recited in claim 1, wherein the at least one twiddle-factor multiplier comprises at least one of a set, the set comprising a multiplier coupled to at least one memory and a multiplexer coupled to a plurality of multipliers.

7. The apparatus recited in claim 1, configured to perform matched filtering for Golay codes having a plurality of lengths.

8. The apparatus recited in claim 1, configured as a parallel processor.

9. The apparatus recited in claim 1, configured for performing packet detection and data demodulation of at least one of a set of signals comprising single-carrier signals and OFDM signals.

10. The apparatus recited in claim 1, configured for generating a signal for transmission and for receiving a transmitted signal.

11. A method for performing both Fourier transform processing and Golay code processing, the method comprising:

providing for a plurality of processing steps, each of the processing steps comprising;

providing for delaying at least a first input signal,

providing for multiplying at least a second input signal by at least one seed-vector value for producing at least one scaled input signal value, and

providing for selecting at least one signal for at least one of delaying and multiplying with respect to at least one predetermined operating mode; and

providing for multiplying at least one signal output from at least one of the plurality of processing steps with at least one twiddle factor when the at least one predetermined operating mode comprises an OFDM mode.

12. The method recited in claim 11, wherein providing for multiplying at least a second input signal by at least one seed-vector value further comprises selecting at least one of a plurality of scaled input signal values.

13. The method recited in claim 11, configured for performing at least one of a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT).

14. The method recited in claim 11, being configurable via at least one control signal to perform at least one of Golay processing and Fourier transform processing.

15. The method recited in claim 11, being configured for Fourier transform processing and bypassing the step of providing for multiplying at least one signal output to perform a fast Walsh-Hadamard transform.

16. The method recited in claim 11, wherein providing for multiplying at least one signal output comprises retrieving the at least one twiddle factor from at least one memory.

17. The method recited in claim 11, wherein providing for multiplying at least one signal output comprises multiplexing at least one of a plurality of signal values.

18. The method recited in claim 11, configured to perform matched filtering for Golay codes having a plurality of lengths.

19. The method recited in claim 11, configured to perform parallel processing.

20. The method recited in claim 11, configured for performing packet detection and data demodulation of at least one of a set of signals comprising single-carrier signals and OFDM signals.

21. The method recited in claim 11, configured for generating a signal for transmission and for receiving a transmitted signal.

22. A digital computer system programmed to perform the method recited in claim 11

23. A computer-readable medium storing a computer program implementing the method of claim 11.

24. A system configured to perform both Fourier transform processing and Golay code processing, the system comprising:

a multi-stage processing means comprising a plurality of processing stages, each of the processing stages comprising;

at least one delaying means configured for providing a predetermined delay to at least a first input signal,

at least one seed vector insertion means configured for multiplying at least a second input signal by at least one seed-vector value for producing at least one scaled input signal value, and

at least one multiplexing means configurable by at least one control signal for selecting an operating mode of the apparatus; and

at least one twiddle-factor multiplication means coupled to at least one output of at least one of the plurality of processing stages.

25. The system recited in claim 24, wherein each of the processing stages further comprises a multiplexing means coupled to the at least one delaying means and the at least one seed vector insertion means, the multiplexing means configured for selecting at least one of a plurality of scaled input signal values.

26. The system recited in claim 24, configured for performing at least one of a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT).

27. The system recited in claim 24, being configurable via at least one control signal to perform at least one of Golay processing and Fourier transform processing.

28. The system recited in claim 24, being configured for Fourier transform processing and bypassing the at least one twiddle-factor multiplication means to perform a fast Walsh-Hadamard transform.

29. The system recited in claim 24, wherein the at least one twiddle-factor multiplication means comprises at least one of a set, the set comprising a first multiplying means coupled to at least one memory-storage means and a multiplexing means coupled to a second multiplying means.

30. The system recited in claim 24, configured to perform matched filtering for Golay codes having a plurality of lengths.

31. The system recited in claim 24, configured as a parallel processor.

32. The system recited in claim 24, configured for performing packet detection and data demodulation of at least one of a set of signals comprising single-carrier signals and OFDM signals.

33. The system recited in claim 24, configured for generating a signal for transmission and for receiving a transmitted signal.

34. A frequency synthesizer comprising:

an oscillator configured for generating a reference signal, and

a phase-locked-loop (PLL) circuit configured for processing the reference signal to produce a plurality of carrier frequencies, the PLL circuit comprising a feedback loop and a frequency-divider circuit, the frequency-divider circuit configurable for selecting one of the plurality of carrier frequencies.

35. The frequency synthesizer recited in claim 34, further configured to generate analog-to-digital and digital-to-analog clock signals.

36. The frequency synthesizer recited in claim 34, further configured for employing at least one of an integer-power-of-two relationship and a product-of-three relationship between each of the plurality of carrier frequencies and a channel bandwidth.

37. The frequency synthesizer recited in claim 34, further comprising a voltage-controlled oscillator, a low-pass filter, and a phase/frequency detector.

38. The frequency synthesizer recited in claim 34, wherein the frequency-divider circuit comprises at least one high-frequency divider configured to divide a signal frequency by at least one of a set of integers, the set comprising an integer that is a power of two and an integer that is a power of three.

39. The frequency synthesizer recited in claim 34, wherein the frequency-divider circuit comprises at least one programmable low-frequency divider.

40. A frequency synthesis method for generating a carrier frequency, the method comprising:

providing for generating a reference signal, and

providing for comparing the reference signal and a feedback signal to generate a voltage-controlled oscillating signal frequency, providing for frequency-dividing and feeding back the voltage-controlled oscillating signal frequency to produce one of a plurality of carrier frequencies, wherein providing for frequency-dividing is configurable for selecting one of the plurality of carrier frequencies.

41. The method recited in claim 40, further configured to generate analog-to-digital and digital-to-analog clock signals.

42. The method recited in claim 40, further configured for employing at least one of an integer-power-of-two relationship and a product-of-three relationship between each of the plurality of carrier frequencies and a channel bandwidth.

43. The method recited in claim 40, further comprising providing for comparing a feedback frequency with the reference frequency for producing a varying DC-level signal, and employing the varying DC-level signal to control the frequency of a voltage-controlled oscillator signal.

44. The method recited in claim 40, wherein providing for frequency-dividing comprises dividing a signal frequency by at least one of a set of integers, the set comprising an integer that is a power of two and an integer that is a power of three.

45. The method recited in claim 40, wherein providing for frequency-dividing comprises providing for programmable low-frequency dividing.

46. A frequency synthesizing system comprising:

an oscillating means configured for generating a reference signal, and

a phase-locked-loop (PLL) means configured for processing the reference signal to produce a plurality of carrier frequencies, the PLL means comprising a feedback means and a frequency-dividing means, the frequency-dividing means configurable for selecting one of the plurality of carrier frequencies.

47. The system recited in claim 46, further configured to generate analog-to-digital and digital-to-analog clock signals.

48. The system recited in claim 46, further configured for employing at least one of an integer-power-of-two relationship and a product-of-three relationship between each of the plurality of carrier frequencies and a channel bandwidth.

49. The system recited in claim 46, further comprising a voltage-controlled oscillating means, a low-pass filtering means, and a phase/frequency detection means.

50. The system recited in claim 46, wherein the frequency-dividing means comprises at least one high-frequency dividing means configured to divide a signal frequency by at least one of a set of integers, the set comprising an integer that is a power of two and an integer that is a power of three.

51. The system recited in claim 46, wherein the frequency-dividing means comprises at least one programmable low-frequency dividing means.