Concurrent optimization of physical design and operational cycle assignment

• US 20070245272A1
• Filed: 03/15/2005
• Published: 10/18/2007
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Rohe, Andre
• Granted Patent: US 7,496,879 B2
• Time in Patent Office: Days
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In some embodiments, the method concurrently optimizes the assignment of the operations to different operation cycles and different configurable circuits. In some embodiments, the optimization includes moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.

Claims

1. A method of designing a configurable integrated circuit (“

IC”

) with a plurality of configurable circuits, the method comprising;

a) receiving a design having a plurality of different operations for the configurable circuits to perform in different operational cycles; and

b) assigning said operations concurrently to different operational cycles and different configurable circuits.

2. The method of claim 1, wherein the assigning includes concurrently optimizing the assignment of said operations to different operational cycles and different configurable circuits.

3. The method of claim 2, wherein the optimizing comprises moving said operations between different operational cycles and different configurable circuits in order to identify an assignment of said operations that satisfies a set of optimization criteria.

4. The method of claim 3, wherein the moving comprises swapping the operational cycles or configurable circuits to which pairs of operations are assigned.

5. The method of claim 1, wherein the configurable IC is a sub-cycle reconfigurable IC, and the operational cycles are sub-cycles related to a clock cycle.

6. The method of claim 1,

wherein assigning said operations to different configurable circuits comprises assigning a first operation to a first configurable circuit,

wherein assigning the first operation to the first configurable circuit comprises defining a first configuration data set for the first configurable circuit, wherein the first configuration data set is for configuring the first configurable circuit to perform the first operation.

7. The method of claim 6,

wherein the configurable IC is a reconfigurable IC,

wherein each of a plurality of configurable circuits is for reconfiguring multiple times during multiple operational cycles,

wherein defining said first configuration data set for the first configurable circuit comprises defining the first configuration data set as the configuration data set for the first configurable circuit during a first operational cycle.

8. The method of claim 7 further comprising defining a second configuration data set for the first configurable circuit in a second operational cycle, wherein the second configuration data set for configuring the first configurable circuit to perform a second operation during the second operational cycle.

9. The method of claim 8, wherein the configurable circuit is a configurable logic circuit, and the first and second operations are functions performed by the configurable logic circuit.

10. The method of claim 8, wherein the configurable circuit is a configurable interconnect circuit, and the first and second operations are interconnect operations performed by the configurable interconnect circuit.

14. The computer readable medium of claim 1, wherein the set of instructions for assigning includes concurrently a set of instructions for optimizing the assignment of said operations to different operational cycles and different configurable circuits.

15. The computer readable medium of claim 14, wherein the set of instructions for optimizing comprises a set of instructions for moving said operations between different operational cycles and different configurable circuits in order to identify an assignment of said operations that satisfies a set of optimization criteria.

16. The computer readable medium of claim 15, wherein the set of instructions for moving comprises a set of instructions for swapping the operational cycles or configurable circuits to which pairs of operations are assigned.

11. A method of designing a reconfigurable integrated circuit (“

IC”

) that implements an IC design that has a plurality of components, said reconfigurable IC having a plurality of reconfiguration cycles and a plurality of physical locations, the method comprising;

a) assigning the components to physical locations and reconfiguration cycles of the reconfigurable IC,

b) said assigning comprising concurrently optimizing the physical-location and reconfiguration-cycle assignments of the components.

12. The method of claim 11, wherein each reconfigurable circuit can have a new configuration during each reconfiguration cycle.

13. A computer readable medium that stores a computer program for designing a configurable integrated circuit (“

IC”

) with a plurality of configurable circuits, the computer program comprising sets of instructions for;

a) receiving a design having a plurality of different operations for the configurable circuits to perform in different operational cycles; and

b) assigning said operations concurrently to different operational cycles and different configurable circuits.

17. The computer readable medium of claim 13, wherein the configurable IC is a sub-cycle reconfigurable IC, and the operational cycles are sub-cycles related to a clock cycle.

18. The computer readable medium of claim 13,

wherein the set of instructions for assigning said operations to different configurable circuits comprises a set of instructions for assigning a first operation to a first configurable circuit,

wherein the set of instructions for assigning the first operation to the first configurable circuit comprises a set of instructions for defining a first configuration data set for the first configurable circuit,

wherein the first configuration data set is for configuring the first configurable circuit to perform the first operation.

19. The computer readable medium of claim 18,

wherein the configurable IC is a reconfigurable IC,

wherein each of a plurality of configurable circuits is for reconfiguring multiple times during multiple operational cycles,

wherein the set of instructions for defining said first configuration data set for the first configurable circuit comprises a set of instructions for defining the first configuration data set as the configuration data set for the first configurable circuit during a first operational cycle.

20. The computer readable medium of claim 19, wherein the program further comprises a set of instructions for defining a second configuration data set for the first configurable circuit in a second operational cycle, the second configuration data set for configuring the first configurable circuit to perform a second operation during the second operational cycle.