Phase change memory cell with limited switchable volume

• US 20070246748A1
• Filed: 04/25/2006
• Published: 10/25/2007
• Est. Priority Date: 04/25/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Breitwisch, Matthew, Rossnagel, Stephen, Philipp, Jan, Schrott, Alejandro, Lam, Chung
• Granted Patent: US 7,514,705 B2
• Time in Patent Office: Days
• US Class Current: 257/246
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/061 Shaping switching materials
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.

Claims

1. A memory cell comprising:

a dielectric layer, the dielectric layer defining a trench having a wide portion and a narrow portion, the narrow portion substantially narrower than the wide portion; and

a phase change material, the phase change material at least partially filling the wide and narrow portions of the trench, and the phase change material within the narrow portion defining a void;

wherein a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a pulse of electrical current to the memory cell.

4. The memory cell of claim 1, wherein a width of the narrow portion of the trench is less than a prescribed minimum lithographic dimension.

5. The memory cell of claim 1, wherein the memory cell further comprises:

a lower liner, the lower liner contacting the phase change material within the narrow portion of the trench;

a bottom electrical contact, the bottom electrical contact contacting the lower liner;

an upper liner, the upper liner contacting the phase change material within the wide portion of the trench; and

a top electrical contact, the top electrical contact contacting the upper liner;

wherein the bottom and top electrical contacts are adapted to receive the pulse of electrical current applied to the memory cell.

6. The memory cell of claim 5, wherein at least one of the lower and upper liners comprises tantalum nitride or titanium nitride.

7. The memory cell of claim 1, wherein the phase change material within the wide portion of the trench defines a recess in the phase change material, and an electrically conductive material fills at least a portion of the recess.

8. The memory cell of claim 1, wherein the phase change material comprises germanium, antimony, sulfur, selenium or tellurium, or a combination thereof.

9. The memory cell of claim 1, wherein the phase change material comprises a ternary alloy comprising germanium, antimony and tellurium.

10. The memory cell of claim 1, wherein the phase change material comprises a transition metal oxide.

2. The memory cell of claim 2, wherein the portion of the phase change material operative to switch between lower and higher electrical resistance states is located within the narrow portion of the trench.

3. The memory cell of claim 2, wherein the portion of the phase change material operative to switch between lower and higher electrical resistance states is located substantially proximate to at least part of a periphery of the void.

11. An integrated circuit comprising one or more memory cells, at least one of the memory cells comprising a dielectric layer, the dielectric layer defining a trench having a wide portion and a narrow portion, the narrow portion substantially narrower than the wide portion, and a phase change material, the phase change material at at least partially filling the wide and narrow portions of the trench and the phase change material within the narrow portion defining a void, wherein a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a pulse of electrical current to the memory cell

12. The integrated circuit of claim 11, wherein the integrated circuit comprises a random access memory.

13. The integrated circuit of claim 11, wherein the integrated circuit comprises a nonvolatile memory.

14. A method of forming a memory cell, the method comprising the steps of:

forming a dielectric layer, the dielectric layer defining a trench having a wide portion and a narrow portion, the narrow portion substantially narrower than the wide portion; and

forming a phase change material, the phase change material at least partially filling the wide and narrow portions of the trench, and the phase change material within the narrow portion defining a void;

wherein a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a pulse of electrical current to the memory cell

15. The method of claim 14, wherein the step of forming the dielectric layer comprises photolithography and reactive ion etching.

16. The method of claim 14, wherein the step of forming the dielectric layer comprises wet chemical etching.

17. The method of claim 14, wherein the step of forming the dielectric layer comprises forming a void in the dielectric layer.

18. The method of claim 17, wherein the step of forming the dielectric layer comprises reactive ion etching through the void in the dielectric layer.

19. The method of claim 14, wherein the step of forming the phase change material comprises sputter deposition.

20. The method of claim 14, further comprising the steps of:

forming a lower liner, the lower liner contacting the phase change material within the narrow portion of the trench;

forming a bottom electrical contact, the bottom electrical contact contacting the lower liner;

forming an upper liner, the upper liner contacting the phase change material within the wide portion of the trench; and

forming a top electrical contact, the top electrical contact contacting the upper liner;

wherein the bottom and top electrical contacts are adapted to receive the pulse of electrical current applied to the memory cell.