Integrated circuit including power diode

• US 20070246794A1
• Filed: 06/22/2007
• Published: 10/25/2007
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Diodes Incorporated
• Inventors: Rodov, Vladimir, Chang, Paul, Chern, Geeng-Chuan, Ghosh, Prognyan, Hsueh, Wayne
• Granted Patent: US 7,964,933 B2
• Time in Patent Office: Days
• US Class Current: 257/501
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Claims

1. A semiconductor integrated circuit comprising:

a) a semiconductor substrate having material of a first conductivity type,

b) a first region in said substrate in which an integrated circuit is fabricated,

c) a second region in said substrate having material of a second conductivity type in which a power diode is fabricated, and

d) dielectric material between the first region and the second region providing electrical isolation between the first region and the second region.

2. The integrated circuit of claim 1 where the dielectric material comprises silicon oxide formed in a surface of the semiconductor substrate, and the second region includes implanted dopant of a second conductivity type.

3. The integrated circuit of claim 2 wherein the dielectric material comprises silicon oxide.

4. The integrated circuit as defined by claim 1 wherein the second region includes epitaxial semiconductor material grown in a trench in one surface of the substrate, and the dielectric material comprises spacers formed on sidewalls of the trench.

5. The integrated circuit as defined by claim 1 wherein the power diode includes a conductive layer on a surface of the substrate functioning as a first electrode, and a conductive via extending from the surface into the substrate and contacting semiconductor material of the second conductivity type which functions as a second electrode.

6. The integrated circuit as defined by claim 5 wherein the power diode comprises a plurality of MOS source/drain elements and associated gate elements all connected together by the first electrode, a semiconductor layer of a second conductivity type in the second region and in which the plurality of MOS source/drain elements are fabricated, the semiconductor layer being contacted by the second electrode.

7. The integrated circuit as defined by claim 6 wherein each MOS source/drain element is electrically connectable to the semiconductor layer through a channel controlled by a gate element.

8. The integrated circuit as defined by claim 7 wherein each channel is laterally graded under a gate element with a sloped P-N junction separating the channel region from the semiconductor layer.

9. The integrated circuit as defined by claim 8 wherein the P-N junction underlies all of the gate element to provide reduced reverse bias leakage current.

10. The integrated circuit as defined by claim 5 wherein the dielectric material comprises silicon oxide formed in a surface of the semiconductor substrate, and the second region includes implanted dopant of a second conductivity type.

11. The integrated circuit as defined by claim 10 wherein the dielectric material comprises silicon oxide.

12. The integrated circuit as defined by claim 5 wherein the second region includes epitaxial semiconductor material grown in a trench in surface of the substrate, and the dielectric material comprises spacers formed on side walls of the trench.

13. A method of fabricating an integrated circuit including a power diode in a semiconductor body comprising the steps of:

a) providing a semiconductor substrate including a surface layer of first conductivity type.

b) forming a dielectric material in a surface of the semiconductor substrate around a first region in which a power diode is to be fabricated and separated from a second region in which an integrated circuit is to be fabricated,

c) forming semiconductor material of a second conductivity type in the first region,

d) fabricating an integrated circuit in the second region,

e) fabricating a plurality of MOS source/drain elements and associated gate elements in a surface of the device region and in the semiconductor material of second conductivity type,

f) forming a first diode electrode contacting the plurality of MOS source/drain elements and associated gate elements,

g) forming a conductive via from the surface of the device region to the semiconductor material of second conductivity type as a second diode electrode.

14. The method of claim 13 wherein step b) includes forming a trench in the first region, and forming dielectric side wall spacers on the trench, and step c) includes epitaxially growing semiconductor material of second conductivity type in the trench.

15. The method of claim 13 wherein step b) includes forming dielectric material in a surface of the semiconductor substrate, and step c) includes implanting dopant of second conductivity type into the first region.

16. The method as defined by claim 13 and further including the step of:

h) forming a doped guard ring of first conductivity type in the first region abutting the dielectric material.

17. The method as defined by claim 16 and further including the step of:

i) forming a plug of first conductivity type in the first region extending into the semiconductor material of second type.

18. The method as defined by claim 13 wherein step g) includes forming dielectric spacers between the conductive via and the plurality of MOS source/drain elements.

19. The method as defined by claim 13 wherein step d) includes forming a plurality of P wells and a plurality of N wells for CMOS transistors.