MULTI-DIE INDUCTOR

• US 20070246805A1
• Filed: 06/29/2006
• Published: 10/25/2007
• Est. Priority Date: 04/25/2006
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Zhang, Ligang, Czarnowski, John M.
• Application Number:
  US11/427,595
• Publication Number:
  US 20070246805A1
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01F 2017/004 with the coil helically wound around an axis without a core
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01F 27/36 Electric or magnetic shields or screens movable for varying inductance H01F21/10
• CPC Class Codes: H01F 27/363 made of electrically conductive material
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A technique for improving the quality factor of an inductor includes increasing a cross-sectional area of the inductor by increasing a vertical dimension associated with the inductor. An apparatus includes an inductor formed partially in a first integrated circuit die and formed partially in at least a second integrated circuit die. The inductor may be formed partially in at least one interconnect structure between the first integrated circuit die and the second integrated circuit die. In at least one embodiment of the invention, the inductor is self-shielding and is configured to generate a magnetic field in response to a current flowing through coupled conductor portions of the self-shielding inductor. The magnetic field of the self-shielding inductor is substantially confined to a core region of the self-shielding inductor.

Claims

1. An apparatus comprising an inductor formed partially in a first integrated circuit die and formed partially in at least a second integrated circuit die.

2. The apparatus, as recited in claim 1, wherein the inductor is formed partially in at least one interconnect structure between the first integrated circuit die and the second integrated circuit die.

3. The apparatus, as recited in claim 2, wherein the interconnect structure includes one or more conductive bumps.

4. The apparatus, as recited in claim 1, wherein the inductor is formed partially in multiple conductive layers on the first integrated circuit die and partially in multiple conductive layers on the second integrated circuit die.

5. The apparatus, as recited in claim 1, wherein the inductor is self-shielding and configured to generate a magnetic field in response to a current flowing through coupled conductor portions of the self-shielding inductor, the magnetic field being substantially confined to a core region of the self-shielding inductor.

6. The apparatus, as recited in claim 1, wherein the inductor includes a coil of coupled conductor portions, the coil being formed around an axis and the coupled conductor portions substantially enclosing a core region within the coil, the axis being coplanar with cross-sections of the coil and the axis being external to cross-sections of the coil.

7. The apparatus, as recited in claim 1, wherein the inductor is formed by at least a fractional number of turns and at least a bottom turn portion is formed in the first integrated circuit die and at least a top turn portion is formed in the second integrated circuit die.

8. The apparatus, as recited in claim 6, wherein the coil forms a perimeter of a substantially symmetric polygonal center of the self-shielding inductor.

9. The apparatus, as recited in claim 6, wherein the coil comprises:

first, second, third, and fourth portions,

wherein the first portion of the coil is parallel to the second portion of the coil, the first and second portions of the coil being approximately equidistant from the axis, and the first and second portions of the coil being coupled to conduct substantially equal currents in substantially opposite directions, and

wherein the third portion of the coil is parallel to the fourth portion of the coil, the third and fourth portions of the coil being approximately equidistant from the axis, and the third and fourth portions of the coil being coupled to conduct substantially equal currents in substantially opposite directions.

10. The apparatus, as recited in claim 6, wherein substantially equal and substantially opposite magnetic fields are generated parallel to a first plane intersecting the axis in corresponding portions of the core region in response to a current flowing through corresponding coupled conductor portions and substantially equal and substantially opposite magnetic fields are generated parallel to at least a second plane intersecting the axis in corresponding portions of the core region in response to a current flowing through corresponding coupled conductor portions.

11. The apparatus, as recited in claim 1, wherein the second integrated circuit die includes conductive traces on a plastic substrate.

12. The apparatus, as recited in claim 6, wherein a number of turns forming the coil is in a range from one turn to approximately twenty turns, inclusively.

13. The apparatus, as recited in claim 6, wherein less than approximately one complete turn forms the coil.

14. A method of manufacturing comprising:

interconnecting a first integrated circuit die and at least a second integrated circuit die to form an inductor, the first integrated circuit die including first conductor portions of the inductor and the second integrated circuit die including second conductor portions of the inductor.

15. The method, as recited in claim 14, wherein the interconnecting forms electrical connections between the first conductor portions and the second conductor portions.

16. The method, as recited in claim 14, wherein the interconnecting includes forming conductive bumps on at least one of the first integrated circuit die and the second integrated circuit die.

17. The method, as recited in claim 14, wherein the interconnecting includes forming through-substrate interconnect for coupling the first conductor portions to the second conductor portions.

18. The method, as recited in claim 14, wherein the inductor is self-shielding and configured to generate a magnetic field in response to a current flowing through coupled conductor portions, the magnetic field being substantially confined to a core region of the self-shielding inductor.

19. An inductor comprising:

a first portion in a first integrated circuit die;

at least a second portion in a second integrated circuit die; and

means for interconnecting the first portion and the second portion.

20. The inductor, as recited in claim 19, wherein inductor generates a magnetic field in response to a current flowing between a first node and a second node, the magnetic field being substantially confined to a substantially enclosed region of the inductor.

21. The apparatus, as recited in claim 19, further comprising:

means for packaging at least the first integrated circuit, the second integrated circuit and the means for interconnecting.