Stack structure of semiconductor packages and method for fabricating the stack structure

• US 20070246811A1
• Filed: 04/04/2007
• Published: 10/25/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Tsai, Fang-Lin, Tsai, Ho-Yi, Pu, Han-Ping, Hsiao, Cheng-Hsu
• Granted Patent: US 7,855,443 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA

Abstract

A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

Claims

1. A method for fabricating a stack structure of semiconductor packages, the method comprising the steps of:

providing a substrate having a first surface and a second surface opposite to the first surface, wherein a plurality of electrical connection pads and dummy pads are formed on the second surface of the substrate;

mounting and electrically connecting at least one semiconductor chip to the first surface of the substrate;

implanting a plurality of solder balls to the electrical connection pads and the dummy pads of the second surface of the substrate, so as to form an upper semiconductor package; and

providing a fabricated lower semiconductor package comprising a substrate, a semiconductor chip disposed on and electrically connected to the substrate, and an encapsulant formed on the substrate and encapsulating the semiconductor chip, and mounting the upper semiconductor package on the lower semiconductor package, wherein the upper semiconductor package is electrically connected to the substrate of the lower semiconductor package by the solder balls implanted to the electrical connection pads of the upper semiconductor package, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads of the upper semiconductor package, so as to form the stack structure of semiconductor packages.

2. The method of claim 1, wherein the lower semiconductor package further comprises a plurality of solder balls implanted to a surface of the substrate free of being mounted with the semiconductor chip.

3. The method of claim 1, wherein the electrical connection pads are formed in a peripheral portion of the second surface of the substrate of the upper semiconductor package and serve as electrical input/output pads, and the dummy pads are formed on the second surface of the substrate of the upper semiconductor package and are located at positions corresponding to those around the encapsulant of the lower semiconductor package.

4. The method of claim 1, wherein at least one of the dummy pads of the second surface of the substrate of the upper semiconductor package is provided at a position corresponding to that closely adjacent to each edge of the encapsulant of the lower semiconductor package.

5. The method of claim 4, wherein the at least one dummy pad is located at a position corresponding to that closely adjacent to one of a middle portion, one end and two ends of each edge of the encapsulant of the lower semiconductor package.

6. The method of claim 1, wherein the dummy pads of the second surface of the substrate of the upper semiconductor package are located at positions corresponding to those closely adjacent to corners of the encapsulant of the lower semiconductor package and further extended along edges forming the corners of the encapsulant of the lower semiconductor package, such that the solder balls implanted to the dummy pads form a dam structure around each of the corners of the encapsulant of the lower semiconductor package.

7. The method of claim 1, wherein the solder balls implanted to the dummy pads are dimensionally smaller than or equal to the solder balls implanted to the electrical connection pads of the upper semiconductor package.

8. The method of claim 1, wherein the substrate of the lower semiconductor package further comprises a plurality of dummy pads formed thereon and corresponding in position to the dummy pads of the second surface of the substrate of the upper semiconductor package.

9. The method of claim 1, wherein each of the solder balls implanted to the dummy pads of the upper semiconductor package comprises a core portion and a peripheral portion, and the core portions of the solder balls implanted to the dummy pads have a higher melting point than that of the solder balls implanted to the electrical connection pads of the upper semiconductor package.

10. The method of claim 9, wherein the core portion is made of one of copper, lead and polymer, and the peripheral portion is made of a solder material.

11. The method of claim 1, wherein the solder balls implanted to the dummy pads of the upper semiconductor package have a higher melting point than that of the solder balls implanted to the electrical connection pads of the upper semiconductor package.

12. The method of claim 11, wherein the solder balls implanted to the dummy pads of the upper semiconductor package are made of one of high-lead alloy and lead-free alloy.

13. A stack structure of semiconductor packages, comprising:

a lower semiconductor package comprising a substrate, a semiconductor chip mounted on and electrically connected to the substrate, and an encapsulant formed on the substrate and encapsulating the semiconductor chip; and

an upper semiconductor package mounted on the lower semiconductor package, wherein the upper semiconductor package comprises a substrate having a first surface and a second surface opposite to the first surface, a semiconductor chip mounted on and electrically connected to the first surface of the substrate, a plurality of electrical connection pads and dummy pads formed on the second surface of the substrate, and a plurality of solder balls implanted to the electrical connection pads and the dummy pads, wherein the upper semiconductor package is electrically connected to the substrate of the lower semiconductor package by the solder balls implanted to the electrical connection pads of the upper semiconductor package, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads of the upper semiconductor package.

14. The stack structure of semiconductor packages of claim 13, wherein the lower semiconductor package further comprises a plurality of solder balls implanted to a surface of the substrate free of being mounted with the semiconductor chip.

15. The stack structure of semiconductor packages of claim 13, wherein the electrical connection pads are formed in a peripheral portion of the second surface of the substrate of the upper semiconductor package and serve as electrical input/output pads, and the dummy pads are formed on the second surface of the substrate of the upper semiconductor package and are located at positions corresponding to those around the encapsulant of the lower semiconductor package.

16. The stack structure of semiconductor packages of claim 13, wherein at least one of the dummy pads of the second surface of the substrate of the upper semiconductor package is provided at a position corresponding to that closely adjacent to each edge of the encapsulant of the lower semiconductor package.

17. The stack structure of semiconductor packages of claim 16, wherein the at least one dummy pad is located at a position corresponding to that closely adjacent to one of a middle portion, one end and two ends of each edge of the encapsulant of the lower semiconductor package.

18. The stack structure of semiconductor packages of claim 13, wherein the dummy pads of the second surface of the substrate of the upper semiconductor package are located at positions corresponding to those closely adjacent to corners of the encapsulant of the lower semiconductor package and further extended along edges forming the corners of the encapsulant of the lower semiconductor package, such that the solder balls implanted to the dummy pads form a dam structure around each of the corners of the encapsulant of the lower semiconductor package.

19. The stack structure of semiconductor packages of claim 13, wherein the solder balls implanted to the dummy pads are dimensionally smaller than or equal to the solder balls implanted to the electrical connection pads of the upper semiconductor package.

20. The stack structure of semiconductor packages of claim 13, wherein the substrate of the lower semiconductor package further comprises a plurality of dummy pads formed thereon and corresponding in position to the dummy pads of the second surface of the substrate of the upper semiconductor package.

21. The stack structure of semiconductor packages of claim 13, wherein each of the solder balls implanted to the dummy pads of the upper semiconductor package comprises a core portion and a peripheral portion, and the core portions of the solder balls implanted to the dummy pads have a higher melting point than that of the solder balls implanted to the electrical connection pads of the upper semiconductor package.

22. The stack structure of semiconductor packages of claim 21, wherein the core portion is made of one of copper, lead and polymer, and the peripheral portion is made of a solder material.

23. The stack structure of semiconductor packages of claim 13, wherein the solder balls implanted to the dummy pads of the upper semiconductor package have a higher melting point than that of the solder balls implanted to the electrical connection pads of the upper semiconductor package.

24. The stack structure of semiconductor packages of claim 23, wherein the solder balls implanted to the dummy pads of the upper semiconductor package are made of one of high-lead alloy and lead-free alloy.