Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication

• US 20070246819A1
• Filed: 04/24/2006
• Published: 10/25/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wood, Alan, Hembree, David
• Granted Patent: US 7,659,612 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
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• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48847 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4899 : Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
• CPC Class Codes: H01L 2224/48992 : Reinforcing structures
• CPC Class Codes: H01L 2224/78301 : Capillary
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• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
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• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
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• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
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• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Claims

1. A semiconductor component comprising:

a substrate having a first side, a substrate contact on the first side, a second side, and a via extending through the substrate from the first side to the second side;

a wire in the via attached to the substrate contact;

a first contact on the wire proximate to the first side;

a second contact on the wire proximate to the second side; and

a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

2. The semiconductor component of claim 1 wherein the via extends through the substrate contact, and the wire is looped out of the via and bonded to the substrate contact.

3. The semiconductor component of claim 1 further comprising a bonding member on the substrate contact attached to the wire, and wherein the first contact comprises a tip portion of the bonding member unencapsulated by the polymer layer.

4. The semiconductor component of claim 1 wherein the first contact comprise a loop portion of the wire unencapsulated by the polymer layer.

5. The semiconductor component of claim 1 wherein the second contact comprises an end of the wire.

6. The semiconductor component of claim 1 wherein the second contact comprises a bump, a pad, a ball, a projection or a surface on the wire.

7. The semiconductor component of claim 1 wherein the substrate comprises a semiconductor substrate having at least one integrated circuit in electrical communication with the substrate contact.

8. The semiconductor component of claim 1 further comprising a polymer member on the substrate contact supporting a loop portion of the wire.

9. The semiconductor component of claim 1 further comprising at least one second substrate on the substrate having a second through wire interconnect in electrical communication with the through wire interconnect.

10. The semiconductor component of claim 1 further comprising a conductive polymer layer on the substrate electrically connecting the through wire interconnect to a second substrate.

11. The semiconductor component of claim 1 further comprising an insulating layer in the via or on the wire.

12. The semiconductor component of claim 1 further comprising a polymer material in the via surrounding the wire.

13. The semiconductor component of claim 1 wherein the polymer layer extends into the via and surrounds the wire.

14. The semiconductor component of claim 1 further comprising a second polymer layer at least partially encapsulating the second side while leaving the second contact exposed.

15. The semiconductor component of claim 1 further comprising a pad on the first side in electrical communication with the substrate contact.

16. The semiconductor component of claim 1 wherein the first contact comprises a projection on a loop portion of the wire.

17. The semiconductor component of claim 1 wherein the polymer layer substantially encapsulates the first side and peripheral edges of the substrate.

18. The semiconductor component of claim 1 wherein the polymer layer substantially encapsulates the first side and the second side of the substrate.

19. The semiconductor component of claim 1 wherein the polymer layer substantially encapsulates the first side and the wire in the via.

20. The semiconductor component of claim 1 wherein the wire includes a metal surface configured as the first contact or the second contact.

21. A semiconductor component comprising:

a semiconductor substrate having a first side, a substrate contact on the first side, and a second side;

a via in the substrate contact and the substrate extending from the first side to the second side;

a wire in the via bonded to the substrate contact;

a bonding member on the wire and the substrate contact having a portion configured as a first contact; and

a polymer layer on the first side at least partially encapsulating the wire and the bonding member while leaving the first contact exposed.

22. The semiconductor component of claim 21 further comprising a second contact on an end of the wire proximate to the second side.

23. The semiconductor component of claim 22 wherein the second contact comprises a surface, a bump, a ball or a projection on the wire.

24. The semiconductor component of claim 22 further comprising a third contact on the wire comprising a loop portion of the wire proximate to the first side.

25. The semiconductor component of claim 22 wherein the bonding member comprises a stud bump, a double bump, a ball bump, a solder bump or a conductive polymer bump.

26. The semiconductor component of claim 22 wherein the semiconductor substrate comprises a thinned semiconductor die.

27. The semiconductor component of claim 22 wherein the semiconductor substrate comprises a semiconductor wafer.

28. The semiconductor component of claim 22 further comprising an insulating layer in the via or on the wire configured to insulate the wire from the semiconductor substrate.

29. The semiconductor component of claim 22 further comprising a polymer material in the via at least partially encapsulating the wire.

30. The semiconductor component of claim 22 further comprising a polymer member on the substrate contact supporting a loop portion of the wire.

31. The semiconductor component of claim 22 further comprising a second polymer layer on the second side.

32. The semiconductor component of claim 22 wherein the polymer layer extends into the via and secures the wire in the via.

33. The semiconductor component of claim 22 wherein the polymer layer encapsulates five sides of the substrate.

34. A semiconductor component comprising:

a semiconductor substrate having a first side, a second side, an integrated circuit, a substrate contact on the first side in electrical communication with the integrated circuit;

a through wire interconnect on the semiconductor substrate comprising a via through the substrate contact and the substrate to the second side, a wire in the via having a loop portion and a bonded connection with the substrate contact, a bonding member on the wire and the substrate contact having a first contact thereon, and a second contact on the wire in the via proximate to the second side; and

a polymer layer on the first side encapsulating the loop portion while leaving the first contact exposed.

35. The semiconductor component of claim 34 further comprising a polymer material surrounding the wire in the via.

36. The semiconductor component of claim 34 wherein the polymer layer extends into the via and secures the wire in the via.

37. The semiconductor component of claim 34 further comprising at least one second semiconductor substrate on the semiconductor substrate having a second through wire interconnect bonded to the through wire interconnect.

38. The semiconductor component of claim 37 further comprising a conductive polymer layer bonding the second semiconductor substrate to the semiconductor substrate and electrically interconnecting the second through wire interconnect to the through wire interconnect.

39. The semiconductor component of claim 37 wherein the semiconductor substrate comprises a thinned die.

40. The semiconductor component of claim 37 wherein the semiconductor substrate comprises a semiconductor wafer.

41. The semiconductor component of claim 37 wherein the first contact comprises a tip portion of the bonding member.

42. The semiconductor component of claim 37 wherein the first contact comprises a stud bump and the wire is bonded to a tip portion thereof.

43. The semiconductor component of claim 37 wherein the first contact comprises a double bump and the wire is bonded to a center portion thereof.

44. The semiconductor component of claim 37 further comprising a pad on the first side in electrical communication with the substrate contact.

45. The semiconductor component of claim 37 wherein the second contact comprises a surface, a bump, a ball or a projection on the wire.

46. A semiconductor component comprising:

a semiconductor substrate having a first side, a substrate contact on the first side, and a second side;

a via in the substrate contact and the substrate extending from the first side to the second side;

a wire in the via bonded to the substrate contact having a loop portion proximate to the first side;

a polymer member on the substrate contact supporting the loop portion; and

a first contact on the wire.

47. The semiconductor component of claim 46 wherein the first contact comprises an exposed surface of the loop portion.

48. The semiconductor component of claim 46 wherein the first contact comprises a projection or a bump on the loop portion.

49. The semiconductor component of claim 46 wherein the first contact includes a layer configured to enhance wear resistance or penetration of a mating contact on a second semiconductor component.

50. The semiconductor component of claim 46 further comprising a polymer layer on the first side substantially encapsulating the loop portion while leaving the first contact exposed.

51. The semiconductor component of claim 46 further comprising a second contact on an end of the wire proximate to the second side.

52. The semiconductor component of claim 46 further comprising a bonding member on the substrate contact having a tip portion configured as another contact.

53. The semiconductor component of claim 46 wherein the wire is free to move in the via.

54. The semiconductor component of claim 46 wherein the wire is secured to the via by a polymer material in the via.

55. The semiconductor component of claim 46 wherein the wire is secured to the via by a polymer layer on the first side and in the via.

56. A semiconductor component comprising:

a semiconductor substrate having a first side, a second side, an integrated circuit, a substrate contact on the first side in electrical communication with the integrated circuit;

a through wire interconnect on the semiconductor substrate comprising a via through the substrate contact and the substrate to the second side, a wire in the via having a loop portion configured as a first contact and a bonded connection with the substrate contact, and a second contact on an end of the wire proximate to the second side; and

a polymer member on the substrate contact supporting the loop portion.

57. The semiconductor component of claim 56 further comprising a polymer layer on the first side encapsulating the loop portion while leaving the first contact exposed.

58. The semiconductor component of claim 57 wherein the polymer layer encapsulates the first side and peripheral edges of the substrate.

59. The semiconductor component of claim 57 wherein the polymer layer encapsulates the first side and extends into the via securing the wire to the via.

60. The semiconductor component of claim 56 further comprising a second polymer layer encapsulating the second side while leaving the second contact exposed.

61. The semiconductor component of claim 56 further comprising a bonding member on the substrate contact and the bonded connection.

62. The semiconductor component of claim 56 wherein the semiconductor substrate comprises a thinned semiconductor die or wafer.

63. A semiconductor system comprising:

a first substrate having a first side, a second side, a substrate contact on the first side, and a via extending through the substrate contact and the substrate from the first side to the second side;

a through wire interconnect on the first substrate comprising a wire in the via bonded to the substrate contact, a first contact on the wire proximate to the first side, a second contact on the wire proximate to the second side, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed; and

at least one second substrate stacked on the first substrate having a second through wire interconnect electrically connected to the first contact or to the second contact.

64. The semiconductor system of claim 63 wherein the first substrate and the second substrate comprise thinned semiconductor dice or thinned semiconductor wafers.

65. The semiconductor system of claim 63 wherein the first substrate comprises a thinned semiconductor die and the second substrate comprises a semiconductor wafer.

66. The semiconductor system of claim 63 further comprising an anisotropic conductive polymer film attaching the second substrate to the first substrate and electrically connecting the second through wire interconnect to the first contact or the second contact.

67. The semiconductor system of claim 63 further comprising a second anisotropic conductive polymer film attaching the first substrate to another substrate and electrically connecting the first through wire interconnect to an electrode on the substrate.

68. A semiconductor system comprising:

a first substrate having a first side, a second side, an integrated circuit, a substrate contact on the first side in electrical communication with the integrated circuit;

a through wire interconnect on the first substrate comprising a via through the substrate contact and the substrate to the second side, a wire in the via having a loop portion configured as a first contact and a bonded connection with the substrate contact, a second contact on an end of the wire proximate to the second side, and a polymer member on the substrate contact supporting the loop portion; and

at least one second substrate stacked on the first substrate having a second through wire interconnect bonded to the first contact or to the second contact.

69. The semiconductor system of claim 68 wherein the first substrate and the second substrate comprise thinned semiconductor dice.

70. The semiconductor system of claim 68 wherein the first substrate comprises a thinned semiconductor die and the second substrate comprises a semiconductor wafer.

71. The semiconductor system of claim 68 wherein the first substrate comprises a first semiconductor wafer and the second substrate comprises a second semiconductor wafer.

72. The semiconductor system of claim 68 further comprising an anisotropic conductive polymer film attaching the second substrate to the first substrate and electrically connecting the second through wire interconnect to the first contact or the second contact.

73. A semiconductor test system comprising:

a device under test comprising a test contact;

a substrate having a first side, a substrate contact on the first side, and a second side; and

a through wire interconnect on the substrate comprising a via in the substrate contact and the substrate extending from the first side to the second side, a wire in the via bonded to the substrate contact having a loop portion proximate to the first side, a polymer member on the substrate contact supporting the loop portion, and a contact on an end of the wire configured to make a temporary electrical connection with the test contact under a biasing force applied by the polymer member.

74. The semiconductor test system of claim 73 wherein the device under test comprises a semiconductor die or an array of dice.

75. The semiconductor test system of claim 73 wherein the device under test comprises a semiconductor wafer.

76. A method for fabricating a semiconductor component comprising:

providing a substrate having a first side, a second side and a substrate contact;

forming a via in the substrate contact and the substrate to the second side;

placing a wire in the via;

forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and

forming a polymer layer on the first side leaving the first contact exposed.

77. The method of claim 76 wherein the forming the polymer layer step comprises a film assisted molding process in which the first contact is protected by a molding film during a molding step.

78. The method of claim 76 further comprising forming a bonding member on the substrate contact attached to the wire, and wherein the first contact comprises a tip portion of the bonding member unencapsulated by the polymer layer.

79. The method of claim 76 wherein the first contact comprise a loop portion of the wire unencapsulated by the polymer layer.

80. The method of claim 76 wherein the second contact comprises an end of the wire.

81. The method of claim 76 wherein the second contact comprises a bump, a pad, a ball or a surface on the wire.

82. The method of claim 76 wherein the substrate comprises a semiconductor substrate having at least one integrated circuit in electrical communication with the substrate contact.

83. The method of claim 76 further comprising forming a polymer member on the substrate contact supporting a loop portion of the wire.

84. The method of claim 76 further comprising attaching at least one second substrate on the substrate having a second through wire interconnect in electrical communication with the through wire interconnect.

85. The method of claim 76 wherein the forming the polymer layer step is performed using a film assisted molding process with the substrate contained on a semiconductor wafer comprising a plurality of substrates.

86. The method of claim 76 wherein the forming the polymer layer step is performed using a film assisted molding process with the substrate contained on a film frame.

87. A method for fabricating a semiconductor component comprising:

providing a substrate having a first side, a second side and a substrate contact;

forming a via in the substrate contact and the substrate to the second side;

placing a wire in the via;

forming a bonding member on the wire and the substrate contact; and

forming a polymer layer on the first side leaving at least a portion of the bonding member exposed.

88. The method of claim 87 wherein the bonding member a stud bump, a ball bump, a double bump, a solder bump or a conductive polymer bump.

89. The method of claim 87 wherein the forming the polymer layer step comprises a film assisted molding process.

90. The method of claim 87 wherein the forming the polymer layer step comprises a film assisted molding process in which a mold film covers the portion of the bonding member.

91. The method of claim 87 wherein the forming the polymer layer step is performed using a film assisted molding process with the substrate contained on a semiconductor wafer comprising a plurality of substrates.

92. The method of claim 87 wherein the forming the polymer layer step is performed using a film assisted molding process with the substrate contained on a film frame.

93. The method of claim 87 further comprising stacking a second substrate on the substrate having a second contact electrically connected to the bonding member.

94. The method of claim 87 further comprising stacking a second substrate on the substrate having a second contact electrically connected to the bonding member using an anisotropic conductive adhesive.

95. The method of claim 87 further comprising stacking a second substrate on the substrate having a second bonding member electrically connected to the bonding member.

96. The method of claim 87 further comprising stacking a second substrate on the substrate having a second wire electrically connected to the wire.

97. The method of claim 87 further comprising forming a polymer material in the via surrounding the wire.

98. The method of claim 87 wherein the forming the polymer layer step deposits the a polymer material in the via surrounding the wire.

99. A method for fabricating a semiconductor component comprising:

providing a semiconductor substrate having an integrated circuit and a substrate contact in electrical communication with the integrated circuit;

forming a via in the contact and the substrate;

placing a wire in the via;

bonding the wire to the substrate contact;

forming a first contact on the first side in electrical communication with the wire;

covering the first contact; and

forming a polymer layer on the first side while the first contact remains covered.

100. The method of claim 99 further comprising forming a second contact on the wire proximate to the second side.

101. The method of claim 99 wherein the covering step and the forming the polymer layer step comprise a film assisted molding process.

102. The method of claim 99 wherein the substrate is contained on a semiconductor wafer during the forming the polymer layer step.

103. The method of claim 99 wherein the substrate is contained on a film frame during the forming the polymer layer step.

104. The method of claim 99 wherein the covering step comprises covering the first contact with a mold film and the forming the polymer layer step comprises film assisted molding.

105. The method of claim 99 wherein the placing step and the bonding step are performed using a bonding capillary.

106. The method of claim 99 further comprising depositing a polymer material in the via and around the wire.

107. The method of claim 99 wherein the forming the polymer layer step deposits polymer material in the via surrounding the wire.

108. The method of claim 99 further comprising forming a bonding member on the wire and on the substrate contact having a portion configured as the first contact.

109. The method of claim 99 further comprising forming a second contact on the wire proximate to the second side.

110. The method of claim 99 further comprising forming a wear resistant or penetrating layer on the second contact.

111. The method of claim 99 further comprising forming a pad on the first side in electrical communication with the substrate contact.

112. A method for fabricating a semiconductor component comprising:

providing a substrate having a first side, a second side and a substrate contact;

forming a via in the substrate contact and the substrate to the second side;

forming a polymer member on the substrate contact; and

placing a wire in the via; and

bonding the wire to the substrate contact with a loop portion thereof supported by the polymer member.

113. The method of claim 112 further comprising forming a contact on the loop portion.

114. The method of claim 112 further comprising forming a metal layer on the loop portion configured to provide wear resistance or oxide penetration.

115. The method of claim 112 further comprising forming a polymer layer on the first side leaving an outer surface of the loop portion exposed.

116. The method of claim 112 further comprising forming a second contact on an end of the wire proximate to the second side.

117. The method of claim 112 wherein the forming the polymer member step comprises depositing, molding or placing a polymer material on the substrate contact.

118. The method of claim 112 wherein the placing and bonding steps are performed using a bonding capillary.

119. A method for fabricating a semiconductor component comprising:

providing a substrate having a first side, a second side and a substrate contact;

forming a via in the substrate contact and the substrate to the second side;

forming a polymer member on the substrate contact;

placing a wire in the via;

bonding the wire to the substrate contact with a loop portion thereof supported by the polymer member; and

forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side.

120. The method of claim 119 further comprising making a temporary electrical connection between the first contact and a test contact with the polymer member providing a biasing force.

121. The method of claim 119 further comprising making a temporary electrical connection between the second contact and a test contact with the polymer member providing a biasing force.

122. The method of claim 119 wherein the first contact comprises an outer surface of the loop portion.

123. The method of claim 119 further comprising making an electrical connection between the loop portion and another contact with the polymer member providing a biasing force.

124. The method of claim 119 wherein the second contact comprises a ball contact on an end of the wire.

125. The method of claim 119 wherein the forming the polymer member step comprises depositing, molding or placing a polymer material on the substrate contact.

126. The method of claim 119 wherein the placing and bonding steps are performed using a bonding capillary.

127. The method of claim 119 further comprising forming an outer layer on the first contact configured to provide wear resistance or oxide penetration.

128. The method of claim 119 further comprising forming an outer layer on the second contact configured to provide wear resistance or oxide penetration.

129. The method of claim 119 further comprising forming a polymer layer on the first side substantially encapsulating the loop portion while leaving the first contact exposed.

130. The method of claim 119 further comprising forming a polymer layer on the second side while leaving the second contact exposed.