Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter

• US 20070247342A1
• Filed: 06/12/2007
• Published: 10/25/2007
• Est. Priority Date: 04/18/2003
• Status: Active Grant

• Current Assignee: EDGEWATER WIRELESS SYSTEMS INC.
• Original Assignee: Edgewater Computer Systems Inc.
• Inventors: Manganaro, Gabriele
• Granted Patent: US 7,403,148 B2
• Time in Patent Office: Days
• US Class Current: 341/150
• CPC Class Codes: H03M 1/0881 by forcing a gradual change from one output level to the next, e.g. soft-start
• CPC Class Codes: H03M 1/72 Sequential conversion in series-connected stages H03M1/68 takes precedence

Abstract

The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

Claims

1. A switched-capacitor digital-to-analog converter comprising:

a plurality of cells, each cell comprising first and second switches switching respective voltages from a source to a charged capacitor; and

respective switch driver circuits each in electrical communication with a respective one of the first and second switches, each switch driver circuit applying a switch control signal to the switch, the switch control signals that turn the switches on differing by an amount determined to equalize the on-state gate-to-source voltage differences of the first and second switches.

2. The converter of claim 1, wherein the switch control signal comprises a gate voltage.

3. The converter of claim 1, wherein the first and second switches are transistor switches.

4. The converter of claim 3, wherein the transistor switches comprise a metal-oxide-semiconductor (MOS) device.

5. A method for data conversion using a switched-capacitor digital-to-analog converter comprising the steps of:

providing a plurality of cells, each cell comprising first and second switches switching respective different voltages from a source to a charged capacitor;

providing respective switch driver circuits each in electrical communication with a respective one of the first and second switches; and

applying respective switch control signals to each of the first and second switches, the switch control signals that turn the switches on differing by an amount determined to equalize the on-state gate-to-source voltage differences of the first and second switches.

6. The method of claim 5, wherein applying the switch control signal comprises using a gate voltage.

7. The method of claim 5, wherein the first and second switches are transistor switches.

8. The method of claim 7, wherein the transistor switches comprise a metal-oxide-semiconductor (MOS) device.

9. A switched-capacitor digital-to-analog converter comprising:

means for respectively switching different voltages from a source to a capacitor in each of a plurality of cells;

means for generating switching control signals to respectively control the switching means in each of the plurality of cells; and

means for respectively differing the switching control signals by an amount determined to equalize the on-state gate-to-source voltage differences of the first and second switches.