LATENCY REDUCTION IN A DISPLAY DEVICE

• US 20070247470A1
• Filed: 07/10/2006
• Published: 10/25/2007
• Est. Priority Date: 04/20/2006
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Wales, Richard T., Graham, Philip R., Dhuey, Michael J.
• Granted Patent: US 8,952,974 B2
• Time in Patent Office: Days
• US Class Current: 345/545
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04L 65/80 Responding to QoS

Abstract

A display device may reduce the latency of the display of a digital signal by reducing the latency that the display device adds to the digital signal. After a digital signal is received by an input module, the signal is stored in a frame buffer as a plurality of pixels. A controller determines the input frame rate of the digital signal and a pixel delay. The controller monitors the frame buffer to determine when the frame buffer has stored a number of pixels greater than or equal to the pixel delay. After the frame buffer contains enough pixels, the controller initiates transmission of the pixels from the frame buffer to a display module. In certain embodiments, the controller initiates transmission of the pixels to the display module before the frame buffer has stored all pixels corresponding to the frame.

Claims

1. A display device for reducing latency comprising:

an input module operable to receive a digital signal having an associated frame rate, the digital signal comprising a frame including a plurality of pixels;

a frame buffer operable to store one or more of the pixels;

a display module operable to receive the pixels and to display the frame; and

a controller operable to determine the frame rate of the digital signal, to determine a pixel delay from the frame rate, to monitor the frame buffer, and, when the frame buffer contains a number of pixels greater than or equal to the pixel delay but less than all pixels corresponding to the frame, to instruct the frame buffer to initiate transmission of the pixels to the display module.

2. The display device of claim 1, wherein the frame buffer has stored less than one percent of the pixels corresponding to the frame when the controller instructs the frame buffer to initiate transmission of the pixels to the display module.

3. The display device of claim 1, wherein the controller determines the pixel delay by:

accessing a minimum pixel table;

comparing the frame rate to one or more industry standard frame rates stored in the minimum pixel table; and

setting the pixel delay to a delay indicated by the industry standard frame rate corresponding to the frame rate.

4. The display device of claim 1, wherein:

the input module receives the digital signal in a first format; and

the display module receives the pixels in a second format, the second format different than the first format.

5. The display device of claim 1, wherein the digital signal comprises a digital video signal in a video conference.

6. The display device of claim 1, wherein the display module comprises one selected from:

a plasma display, a liquid crystal display, organic light emitting diode display, and field emissive device display.

7. The display device of claim 1, wherein the display module is further operable to display the pixels less than or equal to 150 milliseconds after a remote endpoint generates the digital signal.

8. A method for reducing the latency added by a display device comprising:

receiving a digital signal having an associated frame rate at an input module, the digital signal comprising a frame including a plurality of pixels;

storing one or more of the pixels in a frame buffer;

determining the frame rate of the digital signal;

determining a pixel delay from the frame rate;

monitoring the frame buffer;

instructing the frame buffer to initiate transmission of the pixels to the display module when the frame buffer contains a number of pixels greater than or equal to the pixel delay but less than all pixels corresponding to the frame;

receiving the pixels at a display module; and

displaying the frame.

9. The method of claim 8, wherein the frame buffer has stored less than one percent of the pixels corresponding to the frame when the frame buffer is instructed to initiate transmission of the pixels to the display module.

10. The method of claim 8, wherein determining the pixel delay comprises:

accessing a minimum pixel table;

comparing the frame rate to one or more industry standard frame rates stored in the minimum pixel table; and

setting the pixel delay to a delay indicated by the industry standard frame rate corresponding to the frame rate.

11. The method of claim 8, wherein:

the input module receives the digital signal in a first format; and

the display module receives the pixels in a second format, the second format different than the first format.

12. The method of claim 8, wherein the digital signal comprises a digital video signal in a video conference.

13. The method of claim 8, wherein the display module comprises one selected from:

a plasma display, a liquid crystal display, organic light emitting diode display, and field emissive device display.

14. The method of claim 8, wherein displaying the frame on the display module occurs less than or equal to 150 milliseconds after a remote endpoint generates the digital signal.

15. Logic for reducing the latency added by a display device, the logic encoded in media and operable when executed to:

receive a digital signal having an associated frame rate at an input module, the digital signal comprising a frame including a plurality of pixels;

store one or more of the pixels in a frame buffer;

determine the frame rate of the digital signal;

determine a pixel delay from the frame rate;

monitor the frame buffer;

instruct the frame buffer to initiate transmission of the pixels to the display module when the frame buffer contains a number of pixels greater than or equal to the pixel delay but less than all pixels corresponding to the frame;

receive the pixels at a display module; and

display the frame on.

16. The logic of claim 15, wherein the frame buffer has stored less than one percent of the pixels corresponding to the frame when the frame buffer is instructed to initiate transmission of the pixels to the display module.

17. The logic of claim 15, wherein determining the pixel delay comprises:

accessing a minimum pixel table;

comparing the frame rate to one or more industry standard frame rates stored in the minimum pixel table; and

setting the pixel delay to a delay indicated by the industry standard frame rate corresponding to the frame rate.

18. The logic of claim 15, wherein:

the input module receives the digital signal in a first format; and

the display module receives the pixels in a second format, the second format different than the first format.

19. The logic of claim 15, wherein the digital signal comprises a digital video signal in a video conference.

20. The logic of claim 15, wherein the display module comprises one selected from:

a plasma display, a liquid crystal display, organic light emitting diode display, and field emissive device display.

21. The logic of claim 15, wherein displaying the frame on the display module occurs less than or equal to 150 milliseconds after a remote endpoint generates the digital signal.

22. A display device for reducing latency comprising:

means for receiving a digital signal having an associated frame rate at an input module, the digital signal comprising a frame including a plurality of pixels;

means for storing one or more of the pixels in a frame buffer;

means for determining the frame rate of the digital signal;

means for determining a pixel delay from the frame rate;

means for monitoring the frame buffer;

means for instructing the frame buffer to initiate transmission of the pixels to the display module when the frame buffer contains a number of pixels greater than or equal to the pixel delay but less than all pixels corresponding to the frame;

means for receiving the pixels at a display module; and

means for displaying the frame.

23. A conference room for conducting a reduced latency communication comprising:

a user interface operable to receive a user input and to generate an instruction to initiate a communication; and

a conference coordination module operable to receive the instruction from the user interface, to initiate the communication, to receive a digital signal from the remote endpoint, and to communicate the digital signal to a display device;

wherein the display device comprises;

an input module operable to receive a digital signal having an associated frame rate, the digital signal comprising a frame including a plurality of pixels;

a frame buffer operable to store one or more of the pixels;

a display module operable to receive the pixels and to display the frame; and

a controller operable to determine the frame rate of the digital signal, to determine a pixel delay from the frame rate, to monitor the frame buffer, and, when the frame buffer contains a number of pixels greater than or equal to the pixel delay but less than all pixels corresponding to the frame, to instruct the frame buffer to initiate transmission of the pixels to the display module.