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FLEXIBLE AND EFFICIENT MEMORY UTILIZATION FOR HIGH BANDWIDTH RECEIVERS, INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE

  • US 20070247936A1
  • Filed: 04/11/2007
  • Published: 10/25/2007
  • Est. Priority Date: 04/20/2006
  • Status: Active Grant
First Claim
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1. An electronic circuit comprising a signal processing circuit including first and second signal processing blocks coupled in cascade;

  • a memory circuit coupled to and adjustable between the first and second signal processing blocks, said memory circuit having memory spaces, said memory circuit configurable to establish a trade-off of the memory spaces between said first and second signal processing blocks; and

    a configuring circuit operable to configure the trade-off of the memory spaces of said memory circuit.

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