FLEXIBLE AND EFFICIENT MEMORY UTILIZATION FOR HIGH BANDWIDTH RECEIVERS, INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE

• US 20070247936A1
• Filed: 04/11/2007
• Published: 10/25/2007
• Est. Priority Date: 04/20/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Goel, Manish, Lingam, Srinivas, Sella, Assaf, Direnzo, Michael
• Granted Patent: US 8,755,675 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163

Abstract

An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).

Claims

1. An electronic circuit comprising

a signal processing circuit including first and second signal processing blocks coupled in cascade;

a memory circuit coupled to and adjustable between the first and second signal processing blocks, said memory circuit having memory spaces, said memory circuit configurable to establish a trade-off of the memory spaces between said first and second signal processing blocks; and

a configuring circuit operable to configure the trade-off of the memory spaces of said memory circuit.

2. The electronic circuit claimed in claim 1 wherein said signal processing circuit further includes a third signal processing block coupled to and sharing said memory circuit, said memory circuit also configurable to establish the trade-off of the memory spaces between said first, second, and third signal processing blocks.

3. The electronic circuit claimed in claim 1 further comprising a second signal processing circuit, and said memory circuit is further configurable to establish a super-allocation of the memory spaces between said first-named signal processing circuit and said second signal processing circuit.

4. A signal processing device comprising

a signal processing circuit including first and second signal processing blocks;

a memory circuit coupled to and adjustable between the first and second signal processing blocks, said memory circuit having memory spaces, said memory circuit configurable to establish a trade-off of the memory spaces between said first and second signal processing blocks, at least one said signal processing block including taps that couple to said memory circuit; and

a configuring circuit operable to configure said memory circuit and said configuring circuit further having at least one tap selector line coupled to the at least one said signal processing block so that how many taps are selected to couple to said memory circuit is coordinated with the trade-off of the memory spaces in said memory circuit.

5. The signal processing device claimed in claim 4 wherein said taps further provide respective outputs, and said device further has a multiplexer circuit fed by at least two of said respective outputs, and said multiplexer circuit is responsive to said configuration circuit to select one of said respective outputs as output of said multiplexer circuit.

6. The signal processing device claimed in claim 4 wherein said signal processing circuit is operable to provide a signal to said configuring circuit related to an auto-correlation of received pilot data.

7. An electronic circuit comprising

a signal processing circuit including first and second signal processing blocks;

a memory circuit coupled to and adjustable between the first and second signal processing blocks, said memory circuit having memory spaces; and

a control circuit responsive to at least one of said signal processing blocks to dynamically adjust said memory circuit between said first and second signal processing blocks.

8. The electronic circuit claimed in claim 7 wherein said first signal processing block is coupled to provide a Doppler-related signal to said control circuit, and said control circuit is responsive said Doppler-related signal to dynamically establish the trade-off.

9. The electronic circuit claimed in claim 7 wherein said second signal processing block is operable to process a plurality of substantially-concurrent signal streams, the streams being a varying N in number over time, and said second signal processing element is operable to generate a stream number signal related to the varying number N to said control circuit responsive to said stream number signal to dynamically establish the trade-off.

10. The electronic circuit claimed in claim 7 wherein said control circuit is operable, in response to a request for an additional service, to determine that an amount of memory space needed for the additional service exceeds an amount of available memory space in said memory circuit, and to issue a signal rejecting the request for the additional service.

11. A power management circuit comprising

a signal processing circuit including first and second signal processing blocks coupled in cascade;

a memory circuit coupled to and adjustable between the first and second signal processing blocks, the memory having memory spaces, said memory circuit controllable to establish a trade-off of the memory spaces between said first and second signal processing blocks; and

a power control circuit operable to control the trade-off of the memory spaces of said memory circuit and to control the power used by said memory circuit.

12. The power management circuit claimed in claim 11 further comprising a first clock line and a second clock line and wherein said memory circuit includes a multiplexing circuit selectively coupling said first clock line and said second clock line to said memory spaces, said multiplexing circuit responsive to said power control circuit to establish the selective coupling of the first and second clock lines to said memory spaces.

13. The power management circuit claimed in claim 11 wherein said power control circuit is further coupled to said signal processing circuit and operable to control the power used by said signal processing circuit.

14. The power management circuit claimed in claim 11 wherein said power control circuit is responsive to said signal processing circuit to dynamically control the trade-off of the memory spaces of said memory circuit.

15. A digital video receiver comprising

a configurable block operable to trade off Doppler performance with multi-protocol encapsulation forward error correction (MPE-FEC);

and

a microprocessor coupled to said configurable block.

16. The digital video receiver claimed in claim 15 wherein said configurable block includes an adjustable memory circuit configurable to trade off memory space between the Doppler performance and MPE-FEC.

17. The digital video receiver claimed in claim 15 further comprising a display and a handheld enclosure, said display coupled to said microprocessor, said handheld enclosure enclosing said configurable block and said microprocessor.

18. The digital video receiver claimed in claim 15 further comprising a vehicular platform, whereby Doppler signal variations can occur.

19. A digital communication apparatus comprising

a telecommunication signal chain having a physical layer block (PHY) operable to perform automatic retransmission request (ARQ) of packets, and said telecommunication signal chain having a media access controller (MAC) block operable to perform ARQ of packets;

and

an adjustable memory having memory spaces configurably allocated to said PHY ARQ block and to said MAC ARQ block.

20. The digital communication apparatus claimed in claim 19 wherein said telecommunication signal chain has bandwidth categories and is operable to transition between bandwidth categories, and said adjustable memory is responsive to such transition to dynamically reallocate space for said PHY ARQ block and said MAC ARQ block.

21. The digital communication apparatus claimed in claim 20 wherein said adjustable memory is responsive to such transition to dynamically allocate space for said PHY ARQ block depending on a next bandwidth category to which transition is made, and further responsive to trade off memory space for MAC ARQ memory when said PHY ARQ space increases.

22. A process of manufacturing an electronic device comprising

providing an integrated circuit including a signal processing circuit including first and second signal processing blocks coupled in cascade, a memory circuit coupled to and adjustable between the first and second signal processing blocks and configurable to allocate spaces for said first and second signal processing blocks, and a configuring circuit for configuring the trade-off of the memory spaces of said memory circuit;

and

coupling said integrated circuit with a storage circuit having configuration data representing a trade-off for use by the configuring circuit.

23. The process claimed in claim 22 wherein the storage circuit configuration data additionally includes lookup table information for dynamically establishing the trade-off.

24. The process claimed in claim 22 further comprising coupling the integrated circuit with an automotive electronic circuit to manufacture an automotive electronic device.

25. A digital communication apparatus comprising

a telecommunication signal chain having a channel estimation block (CE) and a multi-protocol encapsulation forward error correction block (MPE-FEC);

and

an adjustable memory circuit having memory spaces configurably allocated to the CE block and to the MPE-FEC block.

26. The digital communication apparatus claimed in claim 25 wherein said adjustable memory includes a plural-ported memory having plural ports for both read access and write access and plural busses coupling from said plural ports to at least said CE block and said MPE-FEC block respectively, and further comprising a configuration register circuit coupled to said plural ported memory to configurably allocate memory spaces in said plural-ported memory for use by at least said CE block and said MPE-FEC block.

27. The digital communication apparatus claimed in claim 25 further comprising a configuration circuit coupled to said adjustable memory, and said channel estimation block has taps and said configuration circuit is coupled to said channel estimation block to selectively enable and disable at least one of the taps.

28. A process for use by a business to resolve conflicting requirement sets pertaining to level of Doppler performance and to number of elementary streams of information for video reception, the process comprising

providing a video receiver architecture;

and

configuring the video receiver architecture to establish different product types wherein the same architecture from product-to-product has a product-specific configuration established therein respective to the particular product to which the configuration pertains, the configuration establishing a product-specific trade-off of memory between the level of Doppler performance and the number of elementary streams of information for video reception; and

selling units of at least two of the different product types to customers, whereby the conflicting requirement sets are resolved.

29. A process of operation of an electronic circuit having first and second signal processing blocks and a memory, the process comprising:

configuring a memory circuit to represent a trade-off of the memory spaces between first and second signal processing blocks;

adjusting the memory in response to the configuring to establish the trade-off of the memory spaces between the first and second signal processing blocks; and

operating the signal processing blocks in accordance with the trade-off of the memory spaces.

30. The process claimed in claim 29 further comprising coordinating a tap selection in at least one of the signal processing blocks with the trade-off of the memory spaces.