Semiconductor die package including multiple dies and a common node structure

• US 20070249092A1
• Filed: 04/24/2006
• Published: 10/25/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Klein, Jonathan, Iyer, Venkat
• Granted Patent: US 7,618,896 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/8485 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Claims

1. A semiconductor die package capable of being mounted to a motherboard, the semiconductor die package comprising:

a substrate;

a first semiconductor die mounted on the substrate, wherein the first semiconductor die comprises a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die;

a second semiconductor die mounted on the substrate, wherein second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die; and

a conductive node clip electrically communicating the first output region in the first semiconductor die to the second input region in the second semiconductor die,

wherein the first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

2. The semiconductor die package of claim 1 wherein the substrate is a leadframe structure.

3. The semiconductor die package of claim 1 further comprising a molding material, wherein the molding material covers the first semiconductor die and the second semiconductor die.

4. The semiconductor die package of claim 1 wherein the first semiconductor die comprises a low side MOSFET and the second semiconductor die comprises a high side MOSFET, and wherein the first and second input regions are source regions and the first and second output regions are drain regions.

5. The semiconductor die package of claim 1 further comprising a controller die mounted on the substrate.

6. The semiconductor die package of claim 1 further comprising a molding material, wherein the molding material covers the first semiconductor die and the second semiconductor die, and wherein the conductive node clip is exposed through the molding material and has a surface that is substantially coplanar with an external surface of the molding material.

7. The semiconductor die package of claim 1 wherein the semiconductor die package is a micro-leadframe package (MLP).

8. The semiconductor die package of claim 1 further comprising a second substrate between the second semiconductor die and the conductive node clip.

9. The semiconductor die package of claim 1 wherein the first semiconductor die, the second semiconductor die, and the conductive node clip form parts of a synchronous buck converter circuit.

10. The semiconductor die package of claim 1 wherein the conductive node clip has a step structure.

11. An electrical assembly comprising the semiconductor die package of claim 1.

12. A method for making a semiconductor die package capable of being mounted to a motherboard, the method comprising:

mounting a first semiconductor die to a substrate, wherein the first semiconductor die comprises a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die;

mounting a second semiconductor die to the substrate, wherein second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die; and

attaching a conductive node clip to the first semiconductor die and the second semiconductor die, wherein the conductive node clip electrically communicates the first output region in the first semiconductor die to the second input region in the second semiconductor die.

13. The method of claim 12 further comprising molding a molding material around the first and second semiconductor dies.

14. The method of claim 12 wherein the first semiconductor die, the second semiconductor die, and the conductive node clip form part of a synchronous buck converter circuit.

15. The method of claim 12 wherein the substrate is a leadframe structure.

16. The method of claim 12 further comprising molding a molding material around the first and second semiconductor dies, wherein the molding material has an exterior surface that is substantially coplanar with a surface of the conductive node clip.

17. The method of claim 12 wherein the first semiconductor die comprises a low side MOSFET and the second semiconductor die comprises a high side MOSFET, and wherein the first and second input regions are source regions and the first and second output regions are drain regions.

18. The method of claim 12 wherein the first semiconductor die is part of a first sub-package when the first semiconductor die is mounted to the substrate and the second semiconductor die is part of a second sub-package when the second semiconductor die is mounted to the substrate.

19. The method of claim 12 wherein the conductive node clip comprises copper.

20. The method of claim 12 further comprising mounting a controller die to the substrate.

21. A method for making a semiconductor die package capable of being mounted to a motherboard, the method comprising:

obtaining a first semiconductor die, wherein the first semiconductor die comprises a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die;

obtaining a second semiconductor, wherein second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die;

attaching a conductive node clip to the first semiconductor die and the second semiconductor die, wherein the conductive node clip electrically communicates the first output region in the first semiconductor die to the second input region in the second semiconductor die;

attaching the first semiconductor die, the second semiconductor die, and the conductive node clip to a substrate; and

performing a molding process, thereby forming a package.

22. The method of claim 21 wherein the first and second semiconductor dies are present in separate sub-packages prior to being attached to the conductive node clip.