Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

• US 20070249131A1
• Filed: 04/21/2006
• Published: 10/25/2007
• Est. Priority Date: 04/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Luo, Zhijiong, Lavoie, Christian, Fang, Sunfei, Zhu, Huilong, Sung, Chun-Yung, Jammy, Rajarao, Ng, Hung, Greene, Brian, Wann, Clement, Cabral, Cyril, Allen, Scott, Dezfulian, Kevin
• Granted Patent: US 7,410,852 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Claims

1. A method for forming a metal gate field effect transistor comprising:

forming a metal gate upon a gate dielectric formed over a semiconductor substrate, and using at least the metal gate as a mask to form a source/drain region into the semiconductor substrate, the metal gate being selected to have an opto-thermal annealing radiation reflectivity to avoid opto-thermal annealing damage to the metal gate and metal gate to gate dielectric interface when opto-thermal annealing the source/drain region; and

opto-thermal annealing the source/drain region to form an annealed source/drain region while avoiding opto-thermal annealing damage to the metal gate and metal gate to gate dielectric interface.

2. The method of claim 1 wherein the metal gate comprises a titanium metal.

3. The method of claim 2 wherein the opto-thermal annealing radiation reflectivity is at least about 50 percent.

4. The method of claim 1 wherein the metal gate comprises a metal material selected from the group consisting of aluminum, tungsten, titanium and tantalum, molybdenum, magnesium, platinum, rhenium, rhodium, iridium, and related binary and ternary conductor metallic compounds including nitrides, oxides and silicion containing materials thereof.

5. The method of claim 1 wherein the forming the metal gate comprises forming the metal gate while using a capping layer as a hard mask, and subsequently stripping the capping layer prior to opto-thermal annealing the source/drain region.

6. The method of claim 1 wherein the opto-thermal annealing uses a temperature from about 1000°

to about 1400°

centigrade.

7. The method of claim 1 wherein the opto-thermal annealing uses a time period from about 0.01 to about 100 milliseconds.

8. A method for forming a field effect transistor comprising:

forming a stack layer comprising a silicide forming metal layer contacting a silicon layer over a semiconductor substrate;

forming a source/drain region into the semiconductor substrate while using at least the stack layer as a mask; and

simultaneously opto-thermally annealing the stack layer to form a fully silicided gate electrode and the source/drain region to form an annealed source/drain region.

9. The method of claim 8 wherein the forming the stack layer comprises forming the silicide forming metal layer upon the silicon layer.

10. The method of claim 8 wherein the forming the stack layer comprises forming the silicon layer upon the silicide forming metal layer.

11. The method of claim 8 wherein the forming the stack layer comprises forming a pair of silicon layers sandwiching the silicide forming metal layer.

12. The method of claim 8 wherein the forming the stack layer uses a silicide forming metal selected from the group consisting of cobalt, nickel, platinum, tungsten, titanium silicide forming metals and alloys thereof.

13. The method of claim 8 wherein the opto-thermal annealing uses a temperature from about 1000 to about 1400 degrees centigrade and a time period from about 0.01 to about 100 milliseconds.

14. A method for fabricating a field effect transistor comprising:

forming a stack layer comprising a silicide forming metal contacting a silicon layer over a semiconductor substrate;

forming a source/drain region into the semiconductor substrate while using at least the stack layer as a mask;

forming a thermal insulator layer upon the source/drain region;

forming a thermal absorber layer upon the stack layer; and

selectively opto-thermally annealing the stack layer to form a fully silicide gate electrode while not annealing the source/drain region.

15. The method of claim 14 wherein the forming the stack layer comprises forming the silicide forming metal layer upon the silicon layer.

16. The method of claim 14 wherein the forming the stack layer comprises forming the silicon layer upon the silicide forming metal layer.

17. The method of claim 14 wherein the forming the stack layer uses a silicide forming metal selected from the group consisting of cobalt, nickel, platinum, tungsten, titanium and their alloys.

18. The method of claim 14 wherein the opto-thermal annealing uses a temperature from about 1000°

to about 1400°

centigrade.

19. The method of claim 18 wherein the opto-thermal annealing uses a time period from about 0.01 to about 100 milliseconds.

20. The method of claim 14 wherein the thermal absorber layer comprises an amorphous carbon material.