Mixed signal display for a measurement instrument

• US 20070250278A1
• Filed: 04/21/2006
• Published: 10/25/2007
• Est. Priority Date: 04/21/2006
• Status: Active Grant

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Sullivan, Steven
• Granted Patent: US 7,529,641 B2
• Time in Patent Office: Days
• US Class Current: 702/67
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers

Abstract

A mixed signal measurement instrument provides for the display of both analog and logic signal waveforms using a “no dead time” architecture. For a logic signal all trigger events are detected, the logic signal is sampled at a high rate to produce a sampled logic signal data, the sampled logic signal data are delayed to provide a pre-trigger delay and then are drawn in real time in response to the detected trigger events. A FIFO is used to delay the sampled logic signal data, with the position of the trigger event on the display being determined coarsely by an effective depth of the FIFO. The sampled logic signal data may also be compressed into compression codes prior to the FIFO. A fast drawing engine receives the sampled logic signal data from the FIFO as either data samples or compression codes, and draws a logic waveform using four rows of the drawing engine memory—one row for each of four logic states. The vertical position and height of the logic signal waveform on the display is determined when the logic waveform is transferred from the fast drawing engine to a conventional display buffer.

Claims

1. An apparatus for providing a logic waveform display on a mixed signal measurement instrument using a “

no dead time”

architecture comprising;

means for continuously acquiring samples of a logic signal at a high sample rate;

means for detecting each trigger event within the logic signal;

means for delaying the samples for a pre-trigger time to assure a specified number of samples prior to each trigger event;

means for drawing in real time the samples into a waveform memory at a display sample rate to produce a logic waveform; and

means for transferring the logic waveform to a display buffer at a specified vertical location and with a specified amplitude.

2. The apparatus as recited in claim 1 further comprises means for compressing the samples into compression codes for input to the delaying means.

3. The apparatus as recited in claim 1 wherein the drawing means comprises means for logically drawing the samples into four rows of the waveform memory, each row representing one of four states for the logic signal.

4. The apparatus as recited in claim 3 wherein the logically drawing means comprises means for determining the one of the four states within a time interval from consecutive samples.

5. The apparatus as recited in claim 2 wherein the drawing means comprises means for logically drawing the compression codes into four rows of the waveform memory, each row representing one of four states of the logic signal.

6. The apparatus as recited in claim 5 the logically drawing means comprises means for determining the one of the four states from each of the compression codes.

7. The apparatus as recited in claim 1 wherein the delaying means comprises means for shifting the samples to adjust a position of one of the trigger events relative to the samples on the logic signal display.

8. The apparatus as recited in claim 7 wherein the shifting means comprises:

means for coarse shifting the samples; and

means for fine shifting the samples.

9. The apparatus as recited in claim 8 wherein the coarse shifting means comprises a first-in, first-out (FIFO) buffer having an effective depth determined by an amount that the samples are to be shifted relative to position of the one trigger event.

10. The apparatus as recited in claim 9 wherein the fine shifting means comprises:

a series of flip-flops into which the samples are input; and

a multiplexer for selecting an output from one of the flip-flops to adjust the samples relative to the one trigger signal forwards or backwards in time.

11. The apparatus as recited in claim 1 wherein the delaying means comprises a first-in, first-out (FIFO) buffer having the samples as an input and a delayed version of the samples as an output for input to the drawing means, the FIFO having a width that is a function of the high sample rate relative to a system clock.