Portable high capacity digital data storage device

• US 20070250857A1
• Filed: 06/15/2006
• Published: 10/25/2007
• Est. Priority Date: 04/07/2006
• Status: Abandoned Application

• Current Assignee: Cinegest, Inc.
• Original Assignee: Cinegest, Inc.
• Inventors: Martin, James Brent, Frost-Ruebling, Steven G., van de Loo, Marc J.
• Application Number:
  US11/453,737
• Publication Number:
  US 20070250857A1
• Time in Patent Office: Days
• US Class Current: 725/37
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure

Abstract

A portable data storage device compatible with both standard and high definition digital video cameras is provided. The device includes at least one SDI I/O, and preferably at least one audio I/O and preferably at least one medium speed I/O interface. A device controller takes the high speed serial data, packetizes it, and then sends it out to a plurality of memory modules. Preferably each memory module includes four NAND clusters, each NAND cluster consisting of a flash memory controller and two NAND flash memories. Interposed between the device controller and the memory modules are a plurality of memory controllers, each memory controller controlling a group of memory modules. A user interface is coupled to the device controller, the interface including a display capable of at least two user-selectable orientations, record/playback controls and a four-way directional control pad.

Claims

1. An interface for a data storage device comprising:

a display panel configured to display text;

user accessible means for configuring said display panel into at least a first orientation and a second orientation, wherein said text is flipped 180 degrees between said first orientation and said second orientation; and

a plurality of control buttons, wherein each of said plurality of control buttons controls a playback or recording function of the data storage device; and

wherein said data storage device comprises;

at least one high speed serial digital interface (SDI) video data input;

a primary controller configured to accept serial video data from said high speed SDI video data input, said primary controller comprising a serializer/deserializer (SERDES) circuit, wherein said SERDES circuit converts said serial video data to parallel video data;

a plurality of memory controllers coupled to said primary controller via a plurality of medium speed data channels;

a plurality of NAND clusters coupled to said plurality of memory controllers, wherein said parallel video data is recorded in said plurality of NAND clusters; and

at least one high speed SDI video data output coupled to said primary controller, wherein said primary controller is configured to output said parallel video data recorded in said plurality of NAND clusters via said at least one high speed SDI video data output after said parallel video data is converted to said serial video data by said SERDES circuit.

2. The interface of claim 1, further comprising a device housing, wherein said device housing includes an interface surface at a non-orthogonal angle to a front device housing surface and at a non-orthogonal angle to a top device housing surface.

3. The interface of claim 2, wherein said interface surface contains said display and said plurality of control buttons, and wherein said front device housing surface contains said at least one high speed SDI video data input and said at least one high speed SDI video data output.

4. The interface of claim 3, wherein said interface surface is at a 60 degree angle to said front device housing surface, and wherein said interface surface is at a 30 degree angle to said top device housing surface.

5. The interface of claim 1, wherein each of said plurality of NAND clusters is comprised of a flash memory controller and at least one flash memory.

6. The interface of claim 5, wherein each of said plurality of NAND clusters is comprised of at least two flash memories and said flash memory controller.

7. The interface of claim 1, wherein said plurality of NAND clusters are grouped into a plurality of groups, wherein each group of said plurality of groups is comprised of at least four NAND clusters of said plurality of NAND clusters, wherein each of said plurality of NAND clusters is comprised of a flash memory controller and at least two flash memories, and wherein each group of said plurality of groups corresponds to one of a plurality of individual memory modules.

10. The interface of claim 1, further comprising a battery coupled to said primary controller, said plurality of memory controllers and said plurality of NAND clusters.

11. The interface of claim 10, further comprising a housing, wherein said primary controller, said plurality of memory controllers, said plurality of NAND clusters and said battery are all enclosed within said housing.

12. The interface of claim 10, further comprising a housing, wherein said primary controller, said plurality of memory controllers and said plurality of NAND clusters are all enclosed within said housing and wherein said battery is coupled to said housing with a power cable.

13. The interface of claim 1, wherein said at least one high speed SDI video data input is a high definition (HD) SDI video data input.

14. The interface of claim 1, wherein said at least one high speed SDI video data input is a standard definition (SD) SDI video data input.

15. The interface of claim 1, further comprising at least one audio data input and at least one audio data output.

16. The interface of claim 1, wherein said plurality of medium speed data channels are low voltage differential signaling (LVDS) medium speed data channels.

17. The interface of claim 1, wherein said primary controller is comprised of a first type of field programmable gate array (FPGA) device and wherein each of said plurality of memory controllers is comprised of a second type of FPGA device.

18. The interface of claim 17, wherein said SERDES circuit is external to said first FPGA device.

19. The interface of claim 1, wherein said primary controller is comprised of a first type of application specific integrated circuit (ASIC) device and wherein each of said plurality of memory controllers is comprised of a second type of ASIC device.

20. The interface of claim 19, wherein said SERDES circuit is external to said first ASIC device.

21. The interface of claim 1, further comprising at least two data buffers coupled to said primary controller, wherein said parallel video data is temporarily stored in one of said at least two data buffers before being recorded in said plurality of individual NAND clusters.

22. The interface of claim 21, wherein said at least two data buffers are comprised of double data rate synchronous dynamic random-access memory devices.

23. The interface of claim 1, further comprising at least one NAND flash memory device coupled to said primary controller.

24. The interface of claim 1, further comprising at least one medium speed data output.

25. The interface of claim 1, further comprising at least one medium speed data input/output.

26. The interface of claim 25, wherein said at least one medium speed data input/output is selected from the group consisting of Ethernet, USB, PCIe-Link and SATA interfaces.

27. The interface of claim 1, further comprising at least one high speed data input/output.

28. The interface of claim 27, wherein said at least one high speed data input/output is selected from the group consisting of Ethernet and PCIe-Link interfaces.

29. The interface of claim 1, further comprising at least one four-way directional control pad.

8. The interface of claim I, wherein said plurality of NAND clusters are grouped into a plurality of groups, wherein each group of said plurality of groups is comprised of at least two NAND clusters of said plurality of NAND clusters, and wherein each group of said plurality of groups corresponds to one of a plurality of individual memory modules.

9. The interface of claim 8, further comprising at least one memory circuit board, wherein at least a portion of said plurality of individual memory modules are mounted to said at least one memory circuit board, wherein said portion of said plurality of individual memory modules are grouped according to memory controller such that each group of individual memory modules is coupled to one of said plurality of memory controllers, and wherein individual memory modules of each group are interleaved on said memory circuit board.