Nonvolatile semiconductor memory device and manufacturing method thereof

• US 20070252201A1
• Filed: 01/18/2007
• Published: 11/01/2007
• Est. Priority Date: 03/27/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Mitsuru, Fukuzumi, Yoshiaki, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Matsuoka, Yasuyuki, Nitayama, Akihiro
• Granted Patent: US 7,936,004 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Claims

1. A nonvolatile semiconductor memory device comprising a plurality of memory strings, the memory strings comprising a memory string having a plurality of electrically programmable memory cells connected in series,

wherein the memory string comprises a pillar shaped semiconductor, a first insulation film formed around the pillar shaped semiconductor, a charge storage layer formed around the first insulation film, a second insulation film formed around the charge storage layer, and first to nth electrodes formed around the second insulation film (n is a natural number not less than 2);

and

Wherein the first to the nth electrodes of the memory strings and the first to the nth electrodes of the other memory strings form first to nth conductor layers spread in two dimensional, respectively.

2. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth conductor layers spread in two dimensional are plate-shaped conductor layers, respectively.

3. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the plurality of the memory strings are arranged within a plane being vertical to the pillar shaped semiconductor with a matrix shape.

4. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth conductor layers spread in two dimensional are stacked via an insulation film, respectively, and each of the memory strings is arranged in the first to the nth conductor layers spread in two dimensional with an array shape, respectively.

5. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer is an insulation film.

6. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first insulation film is a silicon oxide film, wherein the charge storage layer silicon nitride layer, and wherein the second insulation film is a silicon oxide film.

7. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shape semiconductor device is either a cylindrical shape or a prism shape.

8. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shape semiconductor is formed vertically on the semiconductor substrate.

9. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the conductor layers forming the first to the nth electrodes of the memory strings are stepwise formed in the edges of the conductor layers.

10. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer is localized between the pillar shape semiconductor and the first to the nth electrodes of the memory strings.

11. The nonvolatile semiconductor memory device as claimed in claim 10, wherein the charge storage layer is a conductor layer.

12. The nonvolatile semiconductor memory device as claimed in claim 1, wherein one of the memory strings comprises a first transistor connected to one end of the memory string and a second transistor connected to the other end of the memory string.

13. The nonvolatile semiconductor memory device as claimed in claim 12, wherein the gate electrode of the first transistor of the memory string and the gate electrode of the first transistor of the other memory string are formed by the same conductor layer.

14. The nonvolatile semiconductor memory device as claimed in claim 12, wherein a diffusion layer part of the semiconductor substrate, in which a source electrode of the first transistor is connected, is an n−

type and the part is directly connected to an n+ diffusion layer.

15. The nonvolatile semiconductor memory device as claimed in claim 12, wherein a diffusion part of the semiconductor substrate, in which a source electrode of the first transistor is connected, is an p−

type and the part is directly connected to a p+ diffusion layer.

16. The nonvolatile semiconductor memory device as claimed in claim 4, wherein an element isolation layer is not formed in the source electrode of the memory stings.

17. The nonvolatile semiconductor memory device as claimed in claim 16, wherein the source electrode of the memory string and the source electrode of the other memory string are electrically insulated by the element isolation layer.

18. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shaped semiconductor is n−

type semiconductor.

19. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the plurality of the memory cells is a depression type transistor.

20. The nonvolatile semiconductor memory device as claimed in claim 14, further comprising:

a poly-silicon layer on the diffusion layer of the semiconductor substrate via an insulation film,

wherein the pillar shaped semiconductor is connected to both of the poly-silicon and the n+ diffusion layer above the semiconductor substrate.

21. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer has a film including nano-crystal.

22. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the memory strings have a symmetry shape to a center axis of the pillar shaped semiconductor.

23. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth electrodes of the memory strings forms word lines, respectively, and wherein the first to the nth electrodes of the memory strings are driven by same word line driving circuit, respectively.

24. The nonvolatile semiconductor memory device as claimed in claim 23, wherein bit lines respectively connected to the drain electrode of the plurality of the memory strings are connected to the same sense amplifier.

25. The nonvolatile semiconductor memory device as claimed in claim 1, wherein a fourth insulation film is formed between the first to the nth electrodes of the memory strings, and wherein the edges of the first to nth electrodes of the memory strings and the edge of the fourth insulation film are stepwise formed.

26. The nonvolatile semiconductor memory device as claimed in claim 1, wherein a fourth insulation film is formed between the first to the nth electrodes of the memory strings, and wherein the parts of the edges of the first to the nth electrodes of the memory strings and the edge of the fourth insulation film are stepwise formed, and the other parts of the edges of the first to nth electrodes of the memory strings and the edge of the fourth insulation film are not stepwise formed.

27. A manufacturing method of a nonvolatile semiconductor memory device comprising:

forming diffusion areas having conductor impurities on a semiconductor substrate;

forming a plurality of first insulation films and conductors in turn above the semiconductor substrates;

forming a plurality of holes in the plurality of the first insulation films and the conductors;

forming a second insulation film on the surface of the holes;

etching the second insulation film at the bottom of the holes; and

forming a plurality of pillar shape semiconductors in the holes, respectively.

28. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 27, further comprising:

forming first to nth electrodes by the plurality of the conductors;

forming the pillar shaped semiconductor, and memory strings, wherein a plurality of memory cells that are electrically programmable are connected in series are connected by a plurality of the second insulation film and the first to the nth electrodes that are in turn formed.

29. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the pluralities of the memory strings are arranged within a plane being vertical to the pillar shaped semiconductor with a matrix shape.

30. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the plurality of the conductors are spread in two dimensional, respectively, and the memory strings are arranged in the plurality of conductor layers with an array shape, respectively.

31. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 27, wherein the second insulation film includes a charge storage layer.

32. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 27, wherein:

a silicon oxide film, a silicon nitride film and a silicon oxide film are stacked in turn in the second insulation film.

33. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 27, wherein the pillar shaped semiconductor is either a cylindrical shape or a prism shape.

34. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 27, wherein the pillar shaped semiconductor is formed vertically on the semiconductor substrate.

35. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the conductor layers forming the first to the nth electrodes of the memory strings are stepwise formed in the edges part of the conductor layers.

36. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein each of the memory strings comprises a first transistor connected to one end of the memory string and a second transistor connected to the other end of the memory string.

37. The manufacturing method of a nonvolatile semiconductor memory device as claimed in claim 36, wherein the gate electrode of the first transistor of the memory string and the gate electrode of the other memory string are formed by the same conductor layer.

38. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 36, wherein a diffusion layer part of the semiconductor substrate in which the source electrode of the first transistor is connected is an n−

type and the diffusion layer is directly connected to the n+ type diffusion layer of the semiconductor substrate.

39. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 36, wherein a diffusion layer part of the semiconductor substrate in which the source electrode of the first transistor is connected is p−

type, and the diffusion layer is directly connected to the p+ type diffusion layer of the semiconductor substrate.

40. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 30, wherein an element isolation layer is not formed among the source electrode of the plurality of the memory strings.

41. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 40, wherein the source electrode of the memory sting and the source electrode of the other memory string are electrically isolated by the element isolation layer.

42. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the pillar shaped semiconductor is n−

type semiconductor.

43. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the plurality of the memory cells is a depression type transistor.

44. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 39, further comprising a poly-silicon layer on the diffusion layer of the semiconductor substrate via an insulation film, wherein the pillar shaped semiconductor is connected to both of the poly-silicon and the n+ diffusion layer above the semiconductor substrate.

45. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 31, wherein the charge storage layer has a film including nano-crystal.

46. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein each of the memory strings have a symmetry shape to a central axis of the pillar shaped semiconductor.

47. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, wherein the first to the nth electrodes of the memory strings form word lines, respectively, wherein the first to the nth electrodes of the memory strings are driven by same word line driving circuit, respectively, wherein and the first to the nth electrodes of the memory strings are connected to same sense amplifier, respectively.

48. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 47, wherein bit lines connected to a drain electrode of the plurality of the memory strings are connected to the same sense amplifier.

49. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 28, further comprising:

manufacturing the first to the nth electrodes of the memory strings and the edge of the first insulation film being stepwise formed.

50. The manufacturing method of the nonvolatile semiconductor memory device as claimed in claim 49, further comprising:

dividing the first to the nth electrodes of the memory strings and the first insulation film of the memory strings to a horizontal direction for the semiconductor substrate.